Generation of hardware machine models from instruction set descriptions

Fauth, A.; Freericks, M.; Knoll, Alois

doi:10.1109/vlsisp.1993.404482

Cited by 19 publications

(13 citation statements)

References 2 publications

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“…The process of building this model is detailed in [10,12]. The machine model, along with 'the datapath constraints and machine-independent transformation rules are given as input to the generic (parameterized) code generator.…”

Section: Retargetingmentioning

confidence: 99%

“…2). Originally designed as a simple means for expressing programming models as found in the usual programmer's manuals, it has turned out to be powerful enough to describe current and future DSP cores -it may even serve as the basis for high-level hardware synthesis [12]. Its main advantage from the programmer's point of view, however, is its compactness combined with its readability, nML is intended for describing arbitrary single instruction stream architectures.…”

Section: Retargetingmentioning

confidence: 99%

“…When retargeting the compiler, the nML analyzer examines the instruction set and the memory description of the target processor and builds a machine model, i.e. a representation of the capabilities and constraints of the machine.The process of building this model is detailed in [10,12]. The machine model, along with 'the datapath constraints and machine-independent transformation rules are given as input to the generic (parameterized) code generator.…”

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confidence: 99%

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Global code selection for directed acyclic graphs

Fauth

Hommel

Knoll

et al. 1994

Lecture Notes in Computer Science

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Abstract. We describe a novel technique for code selection based on data-flow graphs, which arise naturally in the domain of digital signal processing. Code selection is the optimized mapping of abstract operations to partial machine instructions. The presented method performs an important task within the retargetable microcode generator CBC, which was designed to cope with the requirements arising in the context of custom digital signal processor (DSP) programming. The algorithm exploits a graph representation in which control-flow is modeled by scopes. IntroductionIn the domain of medium-throughput digital signal processing, micro-programmable processor cores are frequently chosen for system realization. By adding dedicated hardware (accelerator paths), these cores are tailored to the needs of new applications. Optimized processor modules can be reused, which is a major benefit compared to high-level synthesis [28] where a completely new design is developed for each application. Because of the application-specific add-ons and the rather short lifetimes of a specific design, there is a need for retargetable software development tools, especially code-generators. OverviewIn the next section we will shortly discuss several related approaches to code generation and point out some differences of our system. Section 3 introduces the overall architecture and functionality of the CBC code generator. Section 4 explains the code selection task and the basic techniques used. In section 5 our algorithm is presented. We conclude the paper with experimental results. Points of major differences between our code selection approach and similar tasks in "classic" code generation (CG) are: -Complexity of datapaths. CBC has to deal with highly specialized and optimized datapaths. The hardware units make the efficient execution of frequently used operation sequences possible. Operation patterns for the functional units of these datapaths are much more complex than for standard microprocessors.-Type-handling. DSP algorithms may employ a large variety of different word lengths and numerical types. The hardware operators are restricted to fixed word lengths. A correct mapping must always be found. In most CG work this topic is neglected because language definitions (and hence the compilers) are restricted to "implementation-dependent" types. -Evaluation order. Approaches like [6,7] dealing with code selection assume a fixed evaluation order, which is usually derived from the imperative source code. There is no explicit scheduling phase included in the back-ends. Commonly, register allocation is performed during code selection. Most of the time this is done by graph coloring [4] or "on-the-fly".Parallelism of functional blocks. Most DSP architectures contain several functional units that work in parallel. Therefore, the final code cannot be emitted during or immediately after the code selection phase because partial instructions must be "compacted" into complete instructions at a later stage of compilation exploiting the possible para...

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Section: Retargetingmentioning

confidence: 99%

Section: Retargetingmentioning

confidence: 99%

mentioning

confidence: 99%

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Global code selection for directed acyclic graphs

Fauth

Hommel

Knoll

et al. 1994

Lecture Notes in Computer Science

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“…nML [11] processor instruction set specification language, developed at TU Berlin is an attribute grammar based language used for processor specification. From a nML based processor description, the hardware elements have been generated [12]. The language used in our work Sim-nML is derived from the nML language.…”

Section: Related Workmentioning

confidence: 99%

High level synthesis from Sim-nML processor models

Basu¹,

Moona

16th International Conference on VLSI Design, 2003. Proceedings.

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“…Some of the languages strongly oriented towards the instruction-set are ISDL [7] and nML [6]. The synthesis tool HGEN [12] is used to generate synthesizable Verilog code from an ISDL description. The HDL generator GO from Target Compilers Technologies [13], which is an industrial product, is based on the architecture description language nML.…”

Section: Related Workmentioning

confidence: 99%

A framework for automated and optimized ASIP implementation supporting multiple hardware description languages

Schliebusch¹,

Chattopadhyay²,

Kammler³

et al.

Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.

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Abstract-Architecture Description Languages (ADLs) are widely used to perform design space exploration for Application Specific Instruction Set Processors (ASIPs). While the design space exploration is well supported by numerous tools providing high flexibility and quality, the methodology of automated implementation is limited to simple transformations. Assuming fixed architectural templates, information given in the ADL is directly mapped to a hardware description on Register Transfer Level (RTL). Gate-Level synthesis tools are not able to perform potential optimizations, as the computational complexity grows exponential with the size of the architecture. Information such as exclusiveness, parallelism or boolean relations are spread over multiple modules and therefore hard to determine. In this paper, we present an ASIP synthesis approach from architecture description languages, based on an Intermediate Representation (IR). The IR is the key technology to provide new languageindependent high-level optimizations and to realize different hardware description language backends. The feasibility of our approach is proven in a case-study.

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Generation of hardware machine models from instruction set descriptions

Cited by 19 publications

References 2 publications

Global code selection for directed acyclic graphs

Global code selection for directed acyclic graphs

High level synthesis from Sim-nML processor models

A framework for automated and optimized ASIP implementation supporting multiple hardware description languages

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