A framework for automated and optimized ASIP implementation supporting multiple hardware description languages

Abstract

Abstract-Architecture Description Languages (ADLs) are widely used to perform design space exploration for Application Specific Instruction Set Processors (ASIPs). While the design space exploration is well supported by numerous tools providing high flexibility and quality, the methodology of automated implementation is limited to simple transformations. Assuming fixed architectural templates, information given in the ADL is directly mapped to a hardware description on Register Transfer Level (RTL). Gate-Level synthesis tools are not able to perform potential optimizations, as the computational complexity grows exponential with the size of the architecture. Information such as exclusiveness, parallelism or boolean relations are spread over multiple modules and therefore hard to determine. In this paper, we present an ASIP synthesis approach from architecture description languages, based on an Intermediate Representation (IR). The IR is the key technology to provide new languageindependent high-level optimizations and to realize different hardware description language backends. The feasibility of our approach is proven in a case-study.

C Compilers for ASIPs

“…The RTL hardware model synthesis is based on the so-called unified description layer (UDL) [191]. This enables the integration of optimizations to ensure a sufficient architectural efficiency and transformation to integrate processor features such as JTAG interface and debug mechanism.…”

Retargetable Processor System Integration into Multi-Processor System-on-Chip Platforms

“…Besides the ability to generate the set of software development tools, synthesizable HDL code (both VHDL and Verilog) can be generated automatically from the LISA processor description [104,2]. This comprises both, the control path as well as the data path.…”

“…For the LISA side, there already exists a methodology and tooling to refine a CA processor model for generating an HDL implementation on RT-Level automatically [2]. The methodology includes an intermediate representation [104] on which optimization techniques like resource sharing [115] are applied. The type and semantics of the processor pins that are used to perform the bus accesses on RT-Level are defined in a small processor model independent xml-file [116].…”

Efficient Cached 64 Point FFT Processor Using Floating Point Arithmetic for OFDM Application

“…Energy-efficiency can be determined by containing "Application Specific Instruction Set Processors (ASIPs)" [21,22] and it contains large area. The design flow depends on the Architecture Description Language (ADL) LISA is explained [23] and a framework for automated ASIP implementation is explained [24]. Allow power and area efficient 16-bit wordwidth 64-point radix-2^2 and radix-2^3 pipelined FFT architectures for an OFDM based IEEE 802.11a Wireless Local Area Network (WLAN) baseband is presented [25].…”