Generating FPGA-Accelerated DFT Libraries

Rupnow, Kyle; Underwood, Keith D.; Compton, Katherine

doi:10.1109/fccm.2007.58

Cited by 25 publications

(13 citation statements)

References 17 publications

(28 reference statements)

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“…Further work has been done in implementing FFT cores for FPGAs [8], [10], [11], [3], [9] which can be scaled according to user-specified parameters, including the well regarded Spiral Project [9]. Beyond the radix 2 and 4 Cooley-Tukey seen in the Xilinx implementation, Pease and Fast Hartley Transforms have been implemented in order to achieve a specific tradeoff with regards to performance and resource utilisation [11], [8].…”

Section: Latency-resource Trading Fft Implementations On the Fpgamentioning

confidence: 99%

Exploring the latency-resource trade-off for the Discrete Fourier Transform on the FPGA

Inggs

Thomas

Winberg

2012

22nd International Conference on Field Programmable Logic and Applications (FPL)

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This paper provides a novel way of trading increased resource utilisation for decreased latency when computing a single Discrete Fourier Transform on the FPGA. Analysis conducted on the Cooley-Tukey FFT optimisation shows that it increases the number of operations in the critical path of the transform computation. Consequentially an algorithm is proposed which allows control over the degree to which the Cooley-Tukey optimisation is utilised, trading between resource utilisation and absolute latency. The resource utilisation and latency results for the MyHDL implementation of the proposed algorithm upon the Rhino platform are provided which demonstrate that a practical Pareto curve has been established for a variety of dataset sizes. This implementation is also compared to Xilinx's FFT IP core, providing 14% better latency performance than the manufacturer's implementation albeit at a greater resource cost.

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Section: Latency-resource Trading Fft Implementations On the Fpgamentioning

confidence: 99%

Exploring the latency-resource trade-off for the Discrete Fourier Transform on the FPGA

Inggs

Thomas

Winberg

2012

22nd International Conference on Field Programmable Logic and Applications (FPL)

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“…In architectures, such as those in [17], the performance degrades significantly when data size increases and the data does not fit in the on-chip memory. In these architectures, the bottleneck is the data transfer between the off-chip and on-chip memories.…”

Section: Introductionmentioning

confidence: 98%

“…Several of them are based on the Fast Fourier Transform (FFT) [10]. These include the dedicated FFT processor chips [2,[11][12][13][14], and field programmable gate array (FPGA) based implementations [15][16][17][18][19][20]. As for the FFT chips, their manufacturing cost is quite high, and once a chip is manufactured, its functionality and performance cannot be changed anymore.…”

Section: Introductionmentioning

confidence: 99%

FPGA Architecture for 2D Discrete Fourier Transform Based on 2D Decomposition for Large-sized Data

Kim

Deng

et al. 2010

J Sign Process Syst

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Applications based on Discrete Fourier Transforms (DFT) are extensively used in several areas of signal and digital image processing. Of particular interest is the two-dimensional (2D) DFT which is more computation-and bandwidth-intensive than the one-dimensional (1D) DFT. Traditionally, a 2D DFT is computed using Row-Column (RC) decomposition, where 1D DFTs are computed along the rows followed by 1D DFTs along the columns. Both application This paper is an extension of our paper that appeared in SIPS '09. The added sections are: (1) Impact of large data size on conventional 2D DFT architecture (Section 2.2);(2) Detailed descriptions of the infrastructure components of the FPGA platform (Section 4.2); (3) Detailed description of the automatic 2D DFT system generator (Section 5); (4) Accuracy analysis of the 2D DFT (Section 6.4). specific and reconfigurable hardware have utilized this scheme for high-performance implementations of 2D DFT. However, architectures based on RC decomposition are not efficient for large input size data due to memory bandwidth constraints. In this paper, we propose an efficient architecture to implement 2D DFT for large-sized input data based on a novel 2D decomposition algorithm. This architecture achieves very high throughput by exploiting the inherent parallelism due to the algorithm decomposition and by utilizing the row-wise burst access pattern of the external memory. A high throughput memory interface has been designed to enable maximum utilization of the memory bandwidth. In addition, an automatic system generator is provided for mapping this architecture onto a reconfigurable platform of Xilinx Virtex-5 devices. For a 2K × 2K input size, the proposed architecture is 1.96 times faster than RC decomposition based implementation under the same memory constraints, and also outperforms other existing implementations.

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“…Spiral builds on the Kronecker product framework for the DFT, described in Section 6.1, but extends it to the whole domain of linear transforms. Further, Spiral automates the optimization process outlined in Sections 6.2-6.5 as well as many other optimizations including various forms of parallelization [54,26,79,80]. The fastest FFT implementation shown in Fig.…”

Section: Program Generation For Dft: Spiralmentioning

confidence: 99%

How to Write Fast Numerical Code: A Small Introduction

Chellappa¹,

Franchetti²,

Püschel³

2008

Lecture Notes in Computer Science

Self Cite

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Abstract. The complexity of modern computing platforms has made it extremely difficult to write numerical code that achieves the best possible performance. Straightforward implementations based on algorithms that minimize the operations count often fall short in performance by at least one order of magnitude. This tutorial introduces the reader to a set of general techniques to improve the performance of numerical code, focusing on optimizations for the computer's memory hierarchy. Further, program generators are discussed as a way to reduce the implementation and optimization effort. Two running examples are used to demonstrate these techniques: matrix-matrix multiplication and the discrete Fourier transform.

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Generating FPGA-Accelerated DFT Libraries

Abstract: We present a domain-specific approach to generate highperformance hardware-software partitioned implementations of the discrete Fourier transform (DFT)

Cited by 25 publications

References 17 publications

Exploring the latency-resource trade-off for the Discrete Fourier Transform on the FPGA

Exploring the latency-resource trade-off for the Discrete Fourier Transform on the FPGA

FPGA Architecture for 2D Discrete Fourier Transform Based on 2D Decomposition for Large-sized Data

How to Write Fast Numerical Code: A Small Introduction

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