FPGA Architecture for 2D Discrete Fourier Transform Based on 2D Decomposition for Large-sized Data

Abstract

Applications based on Discrete Fourier Transforms (DFT) are extensively used in several areas of signal and digital image processing. Of particular interest is the two-dimensional (2D) DFT which is more computation-and bandwidth-intensive than the one-dimensional (1D) DFT. Traditionally, a 2D DFT is computed using Row-Column (RC) decomposition, where 1D DFTs are computed along the rows followed by 1D DFTs along the columns. Both application This paper is an extension of our paper that appeared in SIPS '09. The added sections are: (1) Impact of large data size on conventional 2D DFT architecture (Section 2.2);(2) Detailed descriptions of the infrastructure components of the FPGA platform (Section 4.2); (3) Detailed description of the automatic 2D DFT system generator (Section 5); (4) Accuracy analysis of the 2D DFT (Section 6.4). specific and reconfigurable hardware have utilized this scheme for high-performance implementations of 2D DFT. However, architectures based on RC decomposition are not efficient for large input size data due to memory bandwidth constraints. In this paper, we propose an efficient architecture to implement 2D DFT for large-sized input data based on a novel 2D decomposition algorithm. This architecture achieves very high throughput by exploiting the inherent parallelism due to the algorithm decomposition and by utilizing the row-wise burst access pattern of the external memory. A high throughput memory interface has been designed to enable maximum utilization of the memory bandwidth. In addition, an automatic system generator is provided for mapping this architecture onto a reconfigurable platform of Xilinx Virtex-5 devices. For a 2K × 2K input size, the proposed architecture is 1.96 times faster than RC decomposition based implementation under the same memory constraints, and also outperforms other existing implementations.

Memory Bandwidth Efficient Two-Dimensional Fast Fourier Transform Algorithm and Implementation for Large Problem Sizes

“…Some FPGA examples only consider on-chip operation and assume the dataset fits in on-chip memory [10]. FPGA examples that consider off-chip memory interfacing include [7], [4], [5]. Among these implementations, few directly addressed the efficient utilization of the off-chip memory bandwidth.…”

“…Among these implementations, few directly addressed the efficient utilization of the off-chip memory bandwidth. The designs in [7] and [4] do address the memory bandwidth problem but not at the level of detail that includes DRAM row buffer effects. None of the prior FPGA-based implementations targeted double-precision arithmetic which is the required norm for the problem sizes we are concerned with.…”

Implementation of Radon-Framelet Based OFDM on FPGA Platform

“…Step 1: 2D-DFT Subsystem The first three subsystems in the FRAT mapping design perform the 2D-DFT process to matrix A. 2D-DFT is computed using Row-Column (RC) decomposition [11], where the 1D-DFT is computed for each row, and then computed for each column in the resulting matrix. The RC decomposition reported high performance implementation for the 2D-DFT, but it is not favored for large matrix sizes due to the increasing complexity of the design.…”

Modularized architecture of address generation units suitable for real-time processing MR data on an FPGA

“…Much effort has been devoted to developing hardware-accelerated processing systems based on multi-core central processing units (CPUs) or graphics processing units (GPUs), 1 or application-specific integrated circuit (ASIC) and Field Programmable Gate Array (FPGA) chips. [2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17] Among these hardware devices, FPGAs are gradually becoming more widely utilized in MR image processing in real time.…”

“…[7][8][9][10][11][12][13] FFT algorithms also have been designed as IP modules for reconfigurable processors such as FPGAs. 14,15 However, while effective, these processors are generally unable to achieve the performance necessary to process MR data in real time as their architectures are designed without considering the unique characteristics of MR data. One of these characteristics is that with high-speed MRI, time-domain signals typically are spatially encoded irregularly and thus sampled data are irregularly structured with reference to FFT-type computations.…”