Modularized architecture of address generation units suitable for real-time processing MR data on an FPGA

Abstract

In this paper, we describe a modular approach to the design of an Address Generation Unit (AGU). The approach consists of development of a generic Address Generation Core (AGC) as a basic building block and the construction of an AGU from the AGCs. We illustrate this concept with AGUs capable of handling 2D- and 3D-structured data, and as well as their setup for executing 2D and 3D FFT algorithms on a Field Programmable Gate Array (FPGA). The AGUs developed using our proposed method are simple and easily expandable. Furthermore, they can potentially support irregularly structured data which are often generated from the wide variety of pulse sequences in magnetic resonance imaging. Our experimental results show that these AGUs are capable of generating addresses with a user-predefined pattern automatically at the speed of one address per clock cycle and operate at clock rates up to 80 MHz. They can operate concurrently with other processes and thus do not introduce additional operation latencies. Although we focus on applying the developed AGUs to executing 2D and 3D FFT, we expect that the modular design method should have much wider applications.

Parallel 2D FFT implementation on FPGA suitable for real-time MR image processing

“…The data that satisfy this requirement are defined to be regular in structure; otherwise, the data are defined to be irregular. 25 Although the MRI raw data acquired under some basic imaging sequences are regular, modern MRI experiments generate many more irregular data sets. The irregularity of the data not only prevents us from a direct application of the above algorithm but also complicates the data partition and allocation during parallel computations of a 2D FFT.…”