Exploring the latency-resource trade-off for the Discrete Fourier Transform on the FPGA

Abstract

This paper provides a novel way of trading increased resource utilisation for decreased latency when computing a single Discrete Fourier Transform on the FPGA. Analysis conducted on the Cooley-Tukey FFT optimisation shows that it increases the number of operations in the critical path of the transform computation. Consequentially an algorithm is proposed which allows control over the degree to which the Cooley-Tukey optimisation is utilised, trading between resource utilisation and absolute latency. The resource utilisation and latency results for the MyHDL implementation of the proposed algorithm upon the Rhino platform are provided which demonstrate that a practical Pareto curve has been established for a variety of dataset sizes. This implementation is also compared to Xilinx's FFT IP core, providing 14% better latency performance than the manufacturer's implementation albeit at a greater resource cost.

Building a Rhino Harness A Software Defined Radio Toolflow for rapid prototyping upon FPGAs

“…The previous section described the Rhino SDR Toolflow, and this section presents an example of its use in rapidly prototyping an algorithm with applications in SDR [10]. This example application represents an evaluation of the efficacy of the Rhino Toolflow presented in this paper.…”

“…The built-in MyHDL functional simulation capabilities was used to verify and characterise the results produced by the algorithm, while the physical Rhino platform was then further used to verify that the algorithm did in fact perform the computation when implemented in hardware and that the latency performance matched the predictions of the software simulation. Table I presents a comparison between the proposed flexible radix FFT algorithm for a dataset size of 256 inputs and Xilinx FFT IP Core for the same size [10]. Resource utilisation for the proposed algorithm does not compare favourably to the Xilinx Core, however if a DFT equal to or greater than size 32 is used, the proposed algorithm computes the DFT 14% faster than the Xilinx core.…”

“…In light of this trade-off between critical data-path length and resource utilisation, it has been suggested that the CooleyTukey algorithm be generalised to accommodate variable endradices [10]. Hence this generalised flexible radix would take the form that the log 2 ( N D ) butterfly stages a set of DFTs of size D may be computed (as opposed to DFTs of size 2 as Figure 3.…”

“…Hence, provided the end-user is willing to trade the computational resources, greater performance may be achieved. Figure 6 present the Pareto Curves that the proposed flexible radix FFT algorithm offers the end-user for a number of input dataset sizes [10]. Each point on the graph represents an implementation of the algorithm utilising a DFT of varying power of two sizes, from D = 2 to D = 16.…”

“…This example application represents an evaluation of the efficacy of the Rhino Toolflow presented in this paper. Through the use of the Rhino Toolflow, this algorithm was developed and its solution space explored within the context of a larger project [10] over the course of 2 months, illustrating the ease with which it allows for SDR algorithms to be developed.…”