2015
DOI: 10.1007/s11265-015-1057-6
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Measuring and Modeling the Power Consumption of Energy-Efficient FPGA Coprocessors for GEMM and FFT

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Cited by 4 publications
(1 citation statement)
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“…Both classifiers are built with the same hierarchical design principles, but the NRL network could not be implemented on the PYNQ-Z1 board due to insufficient available memory to hold the parameters and intermediate data representations. In order to estimate energy per classification, consumption was assumed to scale linearly with the number of multiply-accumulate (MAC) operations per inference, with 170 pJ per MAC assumed for an energy-efficient FPGA [20]. Latency and throughput estimates are derived directly from Vivado HLS compilation reports.…”
Section: Metricmentioning
confidence: 99%
“…Both classifiers are built with the same hierarchical design principles, but the NRL network could not be implemented on the PYNQ-Z1 board due to insufficient available memory to hold the parameters and intermediate data representations. In order to estimate energy per classification, consumption was assumed to scale linearly with the number of multiply-accumulate (MAC) operations per inference, with 170 pJ per MAC assumed for an energy-efficient FPGA [20]. Latency and throughput estimates are derived directly from Vivado HLS compilation reports.…”
Section: Metricmentioning
confidence: 99%