Generated DSP Cores for Implementation of an OFDM Communication System

Seidel, H.; Matúš, Emil; Cichon, Gordon; Robelly, P.; Bronzel, M.; Fettweis, Gerhard

doi:10.1007/978-3-540-27776-7_37

Cited by 5 publications

(2 citation statements)

References 3 publications

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“…In [9] we have presented an STA DSP for the implementation of an OFDM communications system. Versions of this processor with different levels of SIMD parallelism were synthesized, placed and routed.…”

Section: E Sta Synthesis Resultsmentioning

confidence: 99%

A HW/SW design methodology for embedded SIMD vector signal processors

Robelly

Cichon

Ahlendorf

et al. 2008

IJES

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Abstract-SIMD processors have made their way from supercomputers architectures through embedded real-time signal processing. This trend has been driven by signal processing applications with heavy number-crunching requirements like for example base-band processing on mobile devices.Depending on the data dependencies of algorithms and implementation constraints like real-time, power consumption and die size, the necessary SIMD parallelism can be put into a piece of silicon for a certain application. This poses two challenges: On the one hand, the DSP core design has to be streamlined in such a way that changes on the architecture can be prototyped very fast. On the other hand, the algorithm design and its development have to be done independent of the level of SIMD parallelism available on the DSP in order to enable software reusability.In this paper we report our HW/SW methodology in order to design DSP cores and algorithms that exploit SIMD parallelism. On the hardware development side and taking as a starting point a novel hardware architectural template called STA 1 , we explain how with our approach we automatically generate simulation and hardware models of DSP cores with a scalable level of SIMD parallelism. On the software development side and based on an algebraic model that captures the SIMD computational model, we explain how algorithms can be designed independent of the available SIMD parallelism. We also report how this algebraic model can be easily expressed in Matlab syntax. This enables the automatic code generation from Matlab programs for our family of DSP cores.

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Section: E Sta Synthesis Resultsmentioning

confidence: 99%

A HW/SW design methodology for embedded SIMD vector signal processors

Robelly

Cichon

Ahlendorf

et al. 2008

IJES

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“…Software was developed for OFDM-based transmitter and receiver [10]. We implemented functional blocks similar to those being used in DVB-T/H broadcasting systems.…”

Section: Ofdm-transceivermentioning

confidence: 99%

Hardware/software co-design of a SIMD-DSP-based DVB-T receiver

Seidel

Cichon

Robelly

et al.

Parallel Computing in Electrical Engineering, International Conference On

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The demand for increasing design complexity has to face decreasing design time and design cost issues. Traditional full custom design flows are not reasonable to cope with this challenges. We have developed a design exploration platform which provides access to main chip design parameters beginning from early design stages. With this platform, architecture and hardware/software partitioning failures are correctable with low change cost in a short time. Our designs are based on Synchronous Transfer Architecture SIMD DSP Cores with a tailored instruction set. Automatic Core Generation Tools speed up the design and verification process. In this paper we present our design exploration platform and a use case study for a DVB-T/H like OFDM-Receiver and Transmitter build with our design methodology.-SFB358-Demonstrator 1

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