Synchronous Transfer Architecture (STA)

Cichon, Gordon; Robelly, P.; Seidel, H.; Matúš, Emil; Bronzel, M.; Fettweis, Gerhard

doi:10.1007/978-3-540-27776-7_36

Cited by 36 publications

(34 citation statements)

References 5 publications

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“…This features some resemblance to very large instruction word (VLIW) and transport triggered architectures (TTA) [19]- [21]. A simplification of the TTA architecture is the synchronous transfer architecture (STA) [22], [23], which removes the register file, trigger-ports and queues from the critical path of the TTA architecture, using synchronous communication between modules (somewhat resembling [24]). The assembly instruction thus contains transfer, opcode and explicit trigger signals for each functional module.…”

Section: Final Architecturementioning

confidence: 99%

Soft-Core Dataflow Processor Architecture Optimized for Radar Signal Processing

Broich

Grobler

2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Current radar signal processors lack either performance or flexibility. Custom soft-core processors exhibit potential in high-performance signal processing applications, yet remain relatively unexplored in research literature. In this paper, we use an iterative design methodology to propose a novel softcore streaming processor architecture. The datapaths of this architecture are arranged in a circular pattern, with multiple operands simultaneously flowing between switching multiplexers and functional units each cycle. By explicitly specifying instruction level parallelism and software pipelining, applications can fully exploit the available computational resources. The proposed architecture exceeds the clock cycle performance of a commercial high-end DSP processor by an average factor of 14 over a range of typical operating parameters in a radar signal processor application.

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Section: Final Architecturementioning

confidence: 99%

Soft-Core Dataflow Processor Architecture Optimized for Radar Signal Processing

Broich

Grobler

2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Its distinctive feature might be its CoreManager which is a dedicated run-time scheduler hardware unit (Figure 8). It consumes two Tensilica RISC processors to execute OS and control functions, Six Vector DSPs, an ASIP each for LDPC [26] for low power consumption.…”

Section: Tomahawk Mpsocmentioning

confidence: 99%

State of the art baseband DSP platforms for Software Defined Radio: A survey

Anjum

Ahonen

Garzia

et al. 2011

J Wireless Com Network

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Software Defined Radio (SDR) is an innovative approach which is becoming a more and more promising technology for future mobile handsets. Several proposals in the field of embedded systems have been introduced by different universities and industries to support SDR applications. This article presents an overview of current platforms and analyzes the related architectural choices, the current issues in SDR, as well as potential future trends.

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“…The produced data will in turn be consumed by other basic blocks in the next cycle. Due to the synchronous transference of data between basic blocks we have named the architecture STA [3]. In our concept, basic blocks can be highly optimized data paths or memory blocks.…”

Section: A Sta Architectural Templatementioning

confidence: 99%

“…These stubs can be filled with optimized data paths. As discussed in [3], an slice-based point of view of the design is important to obtain good quality results in the hardware synthesis. Thus, for the generation of the hardware models those basic blocks are recognized, which can be split into slices.…”

Section: Automatic Core Generationmentioning

confidence: 99%

A HW/SW design methodology for embedded SIMD vector signal processors

Robelly

Cichon

Ahlendorf

et al. 2008

IJES

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Abstract-SIMD processors have made their way from supercomputers architectures through embedded real-time signal processing. This trend has been driven by signal processing applications with heavy number-crunching requirements like for example base-band processing on mobile devices.Depending on the data dependencies of algorithms and implementation constraints like real-time, power consumption and die size, the necessary SIMD parallelism can be put into a piece of silicon for a certain application. This poses two challenges: On the one hand, the DSP core design has to be streamlined in such a way that changes on the architecture can be prototyped very fast. On the other hand, the algorithm design and its development have to be done independent of the level of SIMD parallelism available on the DSP in order to enable software reusability.In this paper we report our HW/SW methodology in order to design DSP cores and algorithms that exploit SIMD parallelism. On the hardware development side and taking as a starting point a novel hardware architectural template called STA 1 , we explain how with our approach we automatically generate simulation and hardware models of DSP cores with a scalable level of SIMD parallelism. On the software development side and based on an algebraic model that captures the SIMD computational model, we explain how algorithms can be designed independent of the available SIMD parallelism. We also report how this algebraic model can be easily expressed in Matlab syntax. This enables the automatic code generation from Matlab programs for our family of DSP cores.

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Synchronous Transfer Architecture (STA)

Cited by 36 publications

References 5 publications

Soft-Core Dataflow Processor Architecture Optimized for Radar Signal Processing

Soft-Core Dataflow Processor Architecture Optimized for Radar Signal Processing

State of the art baseband DSP platforms for Software Defined Radio: A survey

A HW/SW design methodology for embedded SIMD vector signal processors

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