GenASM: A High-Performance, Low-Power Approximate String Matching Acceleration Framework for Genome Sequence Analysis

Cali, Damla Senol; Kalsi, Gurpreet S.; Bingöl, Zülal; Fırtına, Can; Subramanian, Lavanya; Kim, Jeremie S.; Ausavarungnirun, Rachata; Alser, Mohammed; Gómez-Luna, Juan; Boroumand, Amirali; Norion, Anant; Scibisz, Allison; Subramoney, Sreenivas; Alkan, Can; Ghose, Saugata; Mutlu, Onur

doi:10.1109/micro50266.2020.00081

Cited by 65 publications

(75 citation statements)

References 146 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…NDPproposals have explored many memory architectures. In the literature, SRAM-based NDP proposals mostly aim to insert logic capabilities to the host's cache memories or to the host's memory controllers [17,19,20,21,22,23,24,58,59,103,106]. This work modify the cache hierarchy trying to avoid moving data from the main memory and cache memories to the host's core.…”

Section: B Memory Architectures and Ndpmentioning

confidence: 99%

“…ASIC and Specialized Units are usually provided to compute determined class of application, for example to efficiently compute certain classes of neural networks, or for operate over huge graphs [17,25,26,27,30,31,47,54,59,64,65,71,77]. In the literature, some works provide specialized hardware to compute such applications.…”

Section: E Specialized Acceleratorsmentioning

confidence: 99%

“…Since this publication, applications ranging from genome string processing to database management systems have all found successful implementations in NDP [29,59,63,69,127,128,129], which increasingly motivates the move to a NDPenabled architecture. All the potential shown by such proposals motivated the creation of commercially available NDP architecture, such as the UPMEM's [82] and the Samsungs' NDP-enabled HBM for artificial intelligence 1 .…”

Section: Related Workmentioning

confidence: 99%

“…The authors propose a general-purpose pattern matching architecture called Impala that implements efficient multi-stride NCA automata processing by addressing these issues. Cali et al [59] presented the GenASM, a framework for approximate string matching designed for genome sequence analysis and used to accelerate various steps in the sequencing process. We also found two works that explore DRAM technology.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Survey on Near-Data Processing: Applications and Architectures

Santos

Moreira

Cordeiro

et al. 2021

JICS

View full text Add to dashboard Cite

One of the main challenges for modern processors is the data transfer between processor and memory. Such data movement implies high latency and high energy consumption. In this context, Near-Data Processing (NDP) proposals have started to gain acceptance as an accelerator device. Such proposals alleviate the memory bottleneck by moving instructions to data whereabouts. The first proposals date back to the 1990s, but it was only in the 2010s that we could observe an increase in papers addressing NDP. It occurred together with the appearance of 3D-stacked chips with logic and memory stacked layers. This survey presents a brief history of these accelerators, focusing on the applications domains migrated to near-data and the proposed architectures. We also introduce a new taxonomy to classify such architectural proposals according to their data distance.

show abstract

Section: B Memory Architectures and Ndpmentioning

confidence: 99%

Section: E Specialized Acceleratorsmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Survey on Near-Data Processing: Applications and Architectures

Santos

Moreira

Cordeiro

et al. 2021

JICS

View full text Add to dashboard Cite

show abstract

“…In NDP, the computational logic close to memory has access to data that resides in main memory with significantly higher memory bandwidth, lower latency, and lower energy consumption than the CPU has in existing systems. There is very high bandwidth available to the cores in the logic layer of 3Dstacked memories, as demonstrated by many past works (e.g., [1,46,59,60,62]- [64,67]- [69,74,76,99,119]). To illustrate this, we use the STREAM Copy [120] workload to measure the peak memory bandwidth the host CPU and an NDP architecture with processing elements in the logic layer of a single 3D-stacked memory (e.g., Hybrid Memory Cube [73]) can leverage.…”

Section: Introductionmentioning

confidence: 99%

DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks

Oliveira¹,

Gómez-Luna

Orosa

et al. 2021

IEEE Access

Self Cite

View full text Add to dashboard Cite

Data movement between the CPU and main memory is a first-order obstacle against improving performance, scalability, and energy efficiency in modern systems. Computer systems employ a range of techniques to reduce overheads tied to data movement, spanning from traditional mechanisms (e.g., deep multi-level cache hierarchies, aggressive hardware prefetchers) to emerging techniques such as Near-Data Processing (NDP), where some computation is moved close to memory. Prior NDP works investigate the root causes of data movement bottlenecks using different profiling methodologies and tools. However, there is still a lack of understanding about the key metrics that can identify different data movement bottlenecks and their relation to traditional and emerging data movement mitigation mechanisms. Our goal is to methodically identify potential sources of data movement over a broad set of applications and to comprehensively compare traditional compute-centric data movement mitigation techniques (e.g., caching and prefetching) to more memory-centric techniques (e.g., NDP), thereby developing a rigorous understanding of the best techniques to mitigate each source of data movement. With this goal in mind, we perform the first large-scale characterization of a wide variety of applications, across a wide range of application domains, to identify fundamental program properties that lead to data movement to/from main memory. We develop the first systematic methodology to classify applications based on the sources contributing to data movement bottlenecks. From our large-scale characterization of 77K functions across 345 applications, we select 144 functions to form the first open-source benchmark suite (DAMOV) for main memory data movement studies. We select a diverse range of functions that (1) represent different types of data movement bottlenecks, and (2) come from a wide range of application domains. Using NDP as a case study, we identify new insights about the different data movement bottlenecks and use these insights to determine the most suitable data movement mitigation mechanism for a particular application. We open-source DAMOV and the complete source code for our new characterization methodology at https: //github.com/CMU-SAFARI/DAMOV.

show abstract