Gated-V/sub dd/: a circuit technique to reduce leakage in deep-submicron cache memories

Powell, Michael D.; Yang, SeungCheol; Falsafi, Babak; Roy, Kaushik; Vijaykumar, T. N.

doi:10.1109/lpe.2000.876763

Cited by 173 publications

(291 citation statements)

References 11 publications

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“…At smaller cache sizes, unused sets can be turned off to reduce the static energy consumption [24]. The miss ratio was used by Yang et al [30] to guide cache reconfiguration, varying the size by masking index bits through a shifting operation.…”

Section: Set-only Reconfigurationmentioning

confidence: 99%

“…This was performed once, before an application started execution. They also used way-shutdown to decrease cache size by turning-off unused ways using the Gated-V dd method [24]. However, they did not address the changes required to the control signals when adding in way-shutdown.…”

Section: Way-only Reconfigurationmentioning

confidence: 99%

“…Yang et al [31] combined configurable set [24] and way [2] architectures to offer a hybrid cache that gives flexibility in terms of size and associativity. Increasing associativity by adding ways but keeping the cache size fixed results in a copying back of previously stored data.…”

Section: Set-and-way Reconfigurationmentioning

confidence: 99%

“…Dynamic cache reconfiguration is not a new topic, having been previously studied by a variety of researchers [1][2][3][7][8][9]24,31,32]. These schemes monitor the miss ratio at run-time, reconfiguring the cache whenever it reaches a certain threshold value.…”

Section: Introductionmentioning

confidence: 99%

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The Smart Cache: An Energy-Efficient Cache Architecture Through Dynamic Adaptation

Sundararajan

Jones

Topham

2012

Int J Parallel Prog

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The demand for low-power embedded systems requires designers to tune processor parameters to avoid excessive energy wastage. Tuning on a per-application or per-application-phase basis allows a greater saving in energy consumption without a noticeable degradation in performance. On-chip caches often consume a significant fraction of the total energy budget and are therefore prime candidates for adaptation.Fixed-configuration caches must be designed to deliver low average memory access times across a wide range of potential applications. However, this can lead to excessive energy consumption for applications that do not require the full capacity or associativity of the cache at all times. Furthermore, in systems where the clock period is constrained by the access times of level-1 caches, the clock frequency for all applications is effectively limited by the cache requirements of the most demanding phase within the most demanding application. This results in both performance and energy efficiency that represents the lowest common denominator across the applications.In this work we present a Set and way Management cache Architecture for Run-Time reconfiguration (SMART cache), a cache architecture that allows reconfiguration in both its size and associativity. Results show the energydelay of the Smart cache is on average 70% and 12% better than the baseline configuration for a two-core and four-core system respectively, with just 2% away from oracle result and also with an overall performance degradation of less than 2% compared with a baseline statically-configured cache.

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Section: Set-only Reconfigurationmentioning

confidence: 99%

Section: Way-only Reconfigurationmentioning

confidence: 99%

Section: Set-and-way Reconfigurationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

The Smart Cache: An Energy-Efficient Cache Architecture Through Dynamic Adaptation

Sundararajan

Jones

Topham

2012

Int J Parallel Prog

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“…Using an inexpensive decaying 4T Temperature sensor [19] we monitor temperature and bias the ground transistor appropriately to yield approximately stable decay times across a wide range of temperatures. 4T decay times converge to a specific value at high temperatures [16] so we only have to adjust decay times at low temperatures. Furthermore, as it is shown in [19] for 4T cells, the decay period of 5T cells is not affected by process variation, except by negligible amounts at low temperatures.…”

Section: Efficient Analog Implementationsmentioning

confidence: 99%

Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches

Κεραμίδας

Xekalakis

2009

Transactions on High-Performance Embedded Architectures and Compilers II

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Abstract. In this paper, we propose a novel approach to reduce dynamic power in set-associative caches that leverages on a leakage-saving proposal, namely Cache Decay. We thus open the possibility to unify dynamic and leakage management in the same framework. The main intuition is that in a decaying cache, dead lines in a set need not be searched. Thus, rather than trying to predict which cache way holds a specific line, we predict, for each way, whether the line could be live in it. We access all the ways that possibly contain the live line and we call this way selection. In contrast to way-prediction, way-selection cannot be wrong: the line is either in the selected ways or not in the cache. The important implication is that we have a fixed hit time -indispensable for both performance and ease-of-implementation reasons. One would expect way-selection to be inferior to sophisticated way-prediction in terms of the total ways accessed, but in fact it can even do better. To achieve this level of accuracy we use Decaying Bloom filters to track only the live lines in ways -dead lines are automatically purged. We offer efficient implementations of such autonomously Decaying Bloom filters, using novel quasi-static cells. Our prediction approach affords us high-accuracy in narrowing the choice of ways for hits as well as the ability to predict misses -a known weakness of way-prediction -thus outperforming sophisticated way-prediction. Furthermore, our approach scales significantly better than way-prediction to higher associativity. We show that decay is a necessary component in this approach -way-selection and Bloom filters alone cannot compete with sophisticated way-prediction. We compare our approach to Multi-MRU and we show that without even considering leakage savings -we surpass it terms of relative power savings and in relative energy-delay in 4-way (9%) and more so in 8-way (20%) and 16-way caches (31%).

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Power-Aware Scheduling for Parallel Security Processors with Analytical Models

Lin

You

Huang

et al. 2005

Lecture Notes in Computer Science

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Abstract. Techniques to reduce power dissipation for embedded systems have recently come into sharp focus in the technology development. Among these techniques, dynamic voltage scaling (DVS), power gating (PG), and multipledomain partitioning are regarded as effective schemes to reduce dynamic and static power. In this paper, we investigate the problem of power-aware scheduling tasks running on a scalable encryption processor, which is equipped with heterogeneous distributed SOC designs and needs the effective integration of the elements of DVS, PG, and the scheduling for correlations of multiple domain resources. We propose a novel heuristic that integrates the utilization of DVS and PG and increases the total energy-saving. Furthermore, we propose an analytic model approach to make an estimate about its performance and energy requirements between different components in systems. These proposed techniques are essential and needed to perform DVS and PG on multiple domain resources which are of correlations. Experiments are done in the prototypical environments for our security processors and the results show that significant energy reductions can be achieved by incorporating our algorithms. 12

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Gated-V/sub dd/: a circuit technique to reduce leakage in deep-submicron cache memories

Cited by 173 publications

References 11 publications

The Smart Cache: An Energy-Efficient Cache Architecture Through Dynamic Adaptation

The Smart Cache: An Energy-Efficient Cache Architecture Through Dynamic Adaptation

Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches

Power-Aware Scheduling for Parallel Security Processors with Analytical Models

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