Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches

Abstract

Abstract. In this paper, we propose a novel approach to reduce dynamic power in set-associative caches that leverages on a leakage-saving proposal, namely Cache Decay. We thus open the possibility to unify dynamic and leakage management in the same framework. The main intuition is that in a decaying cache, dead lines in a set need not be searched. Thus, rather than trying to predict which cache way holds a specific line, we predict, for each way, whether the line could be live in it. We access all the ways that possibly contain the live line and we call this way selection. In contrast to way-prediction, way-selection cannot be wrong: the line is either in the selected ways or not in the cache. The important implication is that we have a fixed hit time -indispensable for both performance and ease-of-implementation reasons. One would expect way-selection to be inferior to sophisticated way-prediction in terms of the total ways accessed, but in fact it can even do better. To achieve this level of accuracy we use Decaying Bloom filters to track only the live lines in ways -dead lines are automatically purged. We offer efficient implementations of such autonomously Decaying Bloom filters, using novel quasi-static cells. Our prediction approach affords us high-accuracy in narrowing the choice of ways for hits as well as the ability to predict misses -a known weakness of way-prediction -thus outperforming sophisticated way-prediction. Furthermore, our approach scales significantly better than way-prediction to higher associativity. We show that decay is a necessary component in this approach -way-selection and Bloom filters alone cannot compete with sophisticated way-prediction. We compare our approach to Multi-MRU and we show that without even considering leakage savings -we surpass it terms of relative power savings and in relative energy-delay in 4-way (9%) and more so in 8-way (20%) and 16-way caches (31%).

A framework for efficient cache resizing

“…However, such approach may be disruptive in our case, because the presented results will be skewed due to different core types (in-order, out-of-order or VLIW machines), core configurations, and memory system configurations (size/associativy of L2/L3 caches). To this end, we refer the reader to previous approaches [1,4,6,7,15,18,19,21], in which it is proved that the energy benefits of cache resizing (by eliminating energy in the cache unused sections) can easily amortize all the resizing overheads (extra structures, additional tag bits, and extra misses to lower level caches) reducing overall processor energy as well. Horizontal resizing.…”

“…In general, hardware-driven resizing techniques are divided to i) techniques that power-down specific cache components i.e., cache lines, ways, or sets and ii) techniques targeting to predict the part of the cache that possible hold the requested data [7]. Our approach can be contrasted more directly to the former techniques.…”

“…Dynamic cache resizing techniques can be classified as software [21] or hardware driven [4,6,7,15,17,18,19]. In general, hardware-driven resizing techniques are divided to i) techniques that power-down specific cache components i.e., cache lines, ways, or sets and ii) techniques targeting to predict the part of the cache that possible hold the requested data [7].…”

“…• They cannot distinguish the reconfiguration events (steady state events) from the transient events (extra events occurring due to a cache downsizing/upsizing) and as a result they tend to be conservative [1,15,17,18,19]. • They propose one-dimensional resizing policies (way-only [1,7,15] or set-only cache resizing [18]) limiting the potential to shape the cache array to the actual requirements of the running applications. Exceptions are the works presented in [17] and [19].…”