Gate Workfunction Engineering of Bulk FinFETs for Sub-50 nm DRAM Cell Transistors

Design Consideration of Bulk FinFETs with Locally-Separated-Channel Structures for Sub-50 nm DRAM Cell Transistors

“…The length of the trench region for channel separation is changed so that the distance between the trench and the source/drain diffusion region is changed. We compare the electrical characteristics of normal channel (NC) bulk FinFET [8], [9] with those of LSC bulk FinFET at given p + /n + poly gate structure. We investigate key properties of proposed devices and provide design guideline through extensive 3-dimensional (3-D) device simulation [15].…”

“…To overcome this problem, p + /n + poly gate FinFETs have been proposed and shown to be effective in reducing I off (< 1 fA/cell) for sub-50 nm DRAM cells [8], [10]. To increase the scalability of FinFETs with a fin body width (W fin ) comparable to L g , it is needed to suppress drain field penetration along the center of the fin body [6], [10]- [12]. The top center region along the fin body can be etched vertically to a depth and the etched region can be filled with oxide, resulting in suppression of the drain field penetration and finally low DIBL [4], [13].…”

“…By changing the gate to p + poly-Si gate, we can increase V th , but I off increases due to increased GIDL current [7]- [9]. To overcome this problem, p + /n + poly gate FinFETs have been proposed and shown to be effective in reducing I off (< 1 fA/cell) for sub-50 nm DRAM cells [8], [10]. To increase the scalability of FinFETs with a fin body width (W fin ) comparable to L g , it is needed to suppress drain field penetration along the center of the fin body [6], [10]- [12].…”