Gate sizing for cell library-based designs

Ketkar, Mahesh; Hu, Jiang

doi:10.1145/1278480.1278690

Cited by 27 publications

(11 citation statements)

References 9 publications

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“…In most cases nearest rounding results in larger fan-out cells and smaller driver cells, consequently the delay pushes out significantly in the end. Our approach to discretizing a continuous sizing solution substantially outperforms nearest rounding by utilizing a branch-and-bound algorithm guided by the continuous solution, similar to [6]. The algorithm is outlined in Fig.…”

Section: Discrete Cell Size Selectionmentioning

confidence: 99%

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Design automation tools and libraries for low power digital design

Rahman¹,

Afonso²,

Tennakoon³

et al. 2010

2010 IEEE Dallas Circuits and Systems Workshop

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Assuming arbitrary (continuous cell sizes) we have achieved global minimization of the total transistor sizes needed to achieve a delay goal, thus minimizing dynamic power (and reducing leakage power). We then developed a feasible branchand-bound algorithm that maps the continuous sizes to the discrete sizes available in the standard cell library. Results show that a well-designed library gives results close to the optimal continuous size results. We developed a new approach to threshold voltage selection, among options available in a cell library. This algorithm is applied after optimal gate size selection, and raises threshold voltages as much as possible while strictly maintaining the delay goal. In addition, we identified the optimal set of (just 8) combinational functions in a physical cell library. These constitute the most power efficient cells needed to implement combinational logic. On the other hand, the synthesis library is much more complex, consisting of cells that are combinations of the physical library cells. This is advantageous since the constituent cells (of a more complex synthesis cell) are placed next to each other in the layout, ensuring minimal wire length between them. Since wire delay is a significant portion of total path delay for contemporary circuits, having complex cells in synthesis is important. But, for power efficiency, the physical cells must be rather simple, with no more than two transistors in series for any cell. The entire cell size and threshold voltage selection flow is efficient, with an ability to handle multi-million-gate commercial designs. After using state-of-the-art commercial synthesis, the application of our design automation tools and library results in a dynamic power reduction of 25-35% and leakage power reduction by 50-70% for large logic blocks.

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Section: Discrete Cell Size Selectionmentioning

confidence: 99%

“…The previous heuristic algorithms perform poorly since local optimization in the vicinity of one gate does not yield acceptable results on a global scale [6]. In addition, there have not been adequate studies to determine the optimal composition of standard cell libraries, in terms of the best set of drive strengths and beta ratios for each function.…”

mentioning

confidence: 99%

Design automation tools and libraries for low power digital design

Rahman¹,

Afonso²,

Tennakoon³

et al. 2010

2010 IEEE Dallas Circuits and Systems Workshop

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“…To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. IEEE/ACM International Conference on Computer-Aided Design (IC-CAD) 2012, November 5-8, 2012, San Jose, California, USA Copyright c 2012 ACM 978-1-4503-1573-9/12/11... $15.00 [13], [14], [15], [5], dynamic programming (DP) [16], [17], [15], multi-direction search [18], brand-and-bound [19], sensitivity-based heuristics [20], [21], [22], [23] and hybrid approaches [19], [5], [17], [9]. However, many of these techniques operate in continuous domain and therefore cannot be directly applied to the CAD problem in real life which is discrete by nature.…”

Section: Introductionmentioning

confidence: 99%

“…Another popular approach to discrete cell-type selection is DP, which may produce optimal solution in a reasonable amount of time. However, DP is known to suffer from fanout reconvergence problem [16] if the circuit is not of tree-structure. A recent break-through in discrete cell-type selection is [15].…”

Section: Introductionmentioning

confidence: 99%

An efficient algorithm for library-based cell-type selection in high-performance low-power designs

Li¹,

Kang²,

et al. 2012

Proceedings of the International Conference on Computer-Aided Design

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In this paper, we present a complete framework for celltype selection in modern high-performance low-power designs with library-based timing model. Our framework can be divided into three stages. First, the best design performance with all possible cell-types is achieved by a Minimum Clock Period Lagrangian Relaxation (MinClock LR) method, which extends the traditional LR approach to conquer the difficulties in discrete scenario. Min-Clock LR fully leverages the prevalent many-core systems as the main body of its workload is composed of independent tasks. Upon a timing-valid design, we solve the timing-constrained power optimization problem by min-cost network flow. Especially, we identify and address the core issues in applying network flow technique to library-based timing model. Finally, a power prune technique is developed to take advantage of the residual slacks due to the conservative network flow construction. Experiments on ISPD 2012 benchmarks show that on average we can save 13% more leakage power on designs with fast timing constraints compared to start-of-theart techniques. Moreover, our algorithm shows a linear empirical runtime , finishing the largest benchmark with one million cells in 1.5 hours.

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“…In [7] Sha used a continuous formulation to obtain continuous sizes that are snapped to the sizes available in the library. Hu [8] allowed the cell sizes to be continuous and then employed dynamic programming to map the solutions to the discrete sizes available in the library.…”

Section: Introductionmentioning

confidence: 99%

Lagrangian relaxation-based Discrete Gate Sizing for leakage power minimization

Livramento

Guth

Güntzel

et al. 2012

2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)

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Discrete Gate Sizing is a commonly used optimization technique for leakage power minimization subject to timing constraints. Basically, sizing corresponds to select, for each gate in a circuit, an implementation option (e.g. a combination of gate size and threshold voltage) available in the cell library such that the leakage power is minimized. A cell library has also max slew and max capacitance constraints which might be considered during optimization. In this work we modify an existing Lagrangian Relaxation formulation considering as constraints not only timing but also max slew and max capacitance constraints. We also adapted the graph model from a state-of-the-art work to reflect our formulation. Compared to an industrial tool, our technique can obtain 33.35% less leakage power, on average, and still meet the considered constraints.

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Gate sizing for cell library-based designs

Cited by 27 publications

References 9 publications

Design automation tools and libraries for low power digital design

Design automation tools and libraries for low power digital design

An efficient algorithm for library-based cell-type selection in high-performance low-power designs

Lagrangian relaxation-based Discrete Gate Sizing for leakage power minimization

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