Lagrangian relaxation-based Discrete Gate Sizing for leakage power minimization

Abstract

Discrete Gate Sizing is a commonly used optimization technique for leakage power minimization subject to timing constraints. Basically, sizing corresponds to select, for each gate in a circuit, an implementation option (e.g. a combination of gate size and threshold voltage) available in the cell library such that the leakage power is minimized. A cell library has also max slew and max capacitance constraints which might be considered during optimization. In this work we modify an existing Lagrangian Relaxation formulation considering as constraints not only timing but also max slew and max capacitance constraints. We also adapted the graph model from a state-of-the-art work to reflect our formulation. Compared to an industrial tool, our technique can obtain 33.35% less leakage power, on average, and still meet the considered constraints.