Gate-level aged timing simulation methodology for hot-carrier reliability assurance

Kawakami, Yoshiyuki; Fang, Jingkun; Yonezawa, Hirokazu; Iwanishi, N.; Wu, Lei; Chen, A. I-Hsien; Koike, N.; Chen, Ping; Yeh, Chih‐Jung; Liu, Zhihong

doi:10.1109/aspdac.2000.835112

Cited by 1 publication

(1 citation statement)

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“…Because these State-of-the-Art tools rely on a transistor-level ageing model and simulation, they are not a sufficient answer to the verification of complex SoCs such that many-core systems: too long simulation time and too high analysis effort by designer. Other approaches propose a verification flow to analyze the effects of HCI on circuit timings at gate level (design netlist), such as [5][6] [7] [8].…”

Section: Introductionmentioning

confidence: 99%

Relation between HCI-induced performance degradation and applications in a RISC processor

Bertolini

Héron

Ventroux

et al. 2012

2012 IEEE 18th International on-Line Testing Symposium (IOLTS)

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Die shrinking combined with the non-ideal scaling of voltage increases the probability of MOS transistors to encounter hot carrier injections (HCI). This failure mechanism causes a performance degradation of digital ICs. The evaluation of timing degradations becomes a must-have to ensure the expected timeto-market and IC lifetime early in the design flow. In this paper, we present a design/verification flow at front-end from which we accurately analyze the impact of instruction-set architecture on processor timings. We show results on a RISC processor named AntX and designed in a 40 nm TSMC technology. Using typicalcase scenarios can increase the maximum operating frequency by 15 % on average compared to a worst-case scenario, while considering the same lifetime. We also identify that the shift operations cause the highest timing degradations along the long processor paths.

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Section: Introductionmentioning

confidence: 99%