2011
DOI: 10.1021/nl104032s
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Gate-Induced Fermi Level Tuning in InP Nanowires at Efficiency Close to the Thermal Limit

Abstract: As downscaling of semiconductor devices continues, one or a few randomly placed dopants may dominate the characteristics. Furthermore, due to the large surface-to-volume ratio of one-dimensional devices, the position of the Fermi level is often determined primarily by surface pinning, regardless of doping level. In this work, we investigate the possibility of tuning the Fermi level dynamically with wrap-around gates, instead of statically setting it using the impurity concentration. This is done using Ω-gated … Show more

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Cited by 21 publications
(34 citation statements)
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References 25 publications
(38 reference statements)
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“…We do not expect significant short-channel effects in our devices, and accordingly, the threshold shift direction is opposite that expected for drain-induced barrier lowering (DIBL). The threshold shift direction is instead indicative of the increased I sd that naturally follows increased V sd at fixed V g , consistent with other nanowire transistors [5,10]. Finally, we comment briefly on the field-effect mobility for our device.…”
Section: Resultssupporting
confidence: 82%
See 1 more Smart Citation
“…We do not expect significant short-channel effects in our devices, and accordingly, the threshold shift direction is opposite that expected for drain-induced barrier lowering (DIBL). The threshold shift direction is instead indicative of the increased I sd that naturally follows increased V sd at fixed V g , consistent with other nanowire transistors [5,10]. Finally, we comment briefly on the field-effect mobility for our device.…”
Section: Resultssupporting
confidence: 82%
“…This is caused by several key challenges for p-type devices including lower intrinsic carrier mobility and difficulties in growth, doping and fabrication of high quality ohmic contacts and gates. Hence III-V nanowire CMOS typically features p-type transistors far less ideal than their n-type counterparts [5,10,11]. Here we present polymer electrolyte gated Be-doped p + -GaAs NWFETs with near-thermal limit gating that point out a path to filling this significant performance gap.…”
Section: Introductionmentioning
confidence: 99%
“…Improved electrostatic control can be achieved by using a top gate [35,118] or creating a vertical transistor with a wrap gate [119].…”
Section: Electrical Methodsmentioning
confidence: 99%
“…We have also demonstrated excellent electrostatic control of charge carriers in wrap-gated intrinsic InP NWs, allowing the Fermi level to be shifted across the entire band gap, inducing both n-type and p-type behavior [3]. By using two gates positioned sequentially along the length of the nanowire and biased with voltages of opposite polarity, we have created an artificial, doping-free p-n junction in which the built-in voltage can be tuned by the applied gate voltages [4].…”
Section: Transparently Wrap-gated Semiconductor Nanowire Arrays For Smentioning
confidence: 98%