GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits

Kunal, Kishor; Dhar, Tonmoy; Madhusudan, Meghna; Poojary, Jitesh; Sharma, Arvind Kumar; Xu, Wenbin; Burns, Steven; Hu, Jiang; Harjani, Ramesh; Sapatnekar, Sachin S.

doi:10.23919/date48585.2020.9116329

Cited by 46 publications

(38 citation statements)

References 18 publications

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“…Five variants of performance driven placement based on Section 4 are tested. They are guided by combinations of PEA vs. CNN [19], SS (Self-sustained learning) vs. transfer learning, and performance cost defined by Equation (17) and defined by Equation (18). To capture the overall circuit performance, a…”

Section: Results On Analog Placementmentioning

confidence: 99%

“…Recently, various machine learning techniques have been explored for analog circuit synthesis [15][16][17][18][19][20]. In [15], GNN (Graph Neural Network) is applied to produce layout templates for passive elements in RF circuits.…”

Section: Introductionmentioning

confidence: 99%

“…Variational auto-encoder is employed in [17] to learn from manual layout and provide routing guidance. The work of [18] makes use of GCN (Graph Convolutional Network) to recognize analog sub-circuits. A CNN (Convolutional Neural Network)-based analog circuit performance model is introduced in [19].…”

Section: Introductionmentioning

confidence: 99%

“…=1 min( , 1) < , where corresponds to Gain, UGF, BW and PM, are their specifications and is a threshold. This is the binary classification version of Equation (18). The main results of self-sustained learning are shown in Table 2.…”

mentioning

confidence: 99%

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A customized graph neural network model for guiding analog IC placement

Li¹,

Lin²,

Madhusudan

et al. 2020

Proceedings of the 39th International Conference on Computer-Aided Design

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Section: Results On Analog Placementmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

mentioning

confidence: 99%

See 2 more Smart Citations

A customized graph neural network model for guiding analog IC placement

Li¹,

Lin²,

Madhusudan

et al. 2020

Proceedings of the 39th International Conference on Computer-Aided Design

Self Cite

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“…Such classification may lose some building blocks, such as the two cascode pairs in Figure 3(b), because M 5 and M 6 miss "cp" the label. Different from [12], we apply multi-label classification [21], as seen in Figure 3(c), in order to completely classify all possible analog building blocks.…”

Section: Multi-label Classification Formulationmentioning

confidence: 99%

Achieving analog layout integrity through learning and migration

Chi

Patyal

Liu

et al. 2020

Proceedings of the 39th International Conference on Computer-Aided Design

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Fully Binarized Graph Convolutional Network Accelerator Based on In‐Memory Computing with Resistive Random‐Access Memory

Zhang,

Li,

Zhang

et al. 2024

Advanced Intelligent Systems

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Artificial intelligence for graph‐structured data has achieved remarkable success in applications such as recommendation systems, social networks, drug discovery, and circuit annotation. Graph convolutional networks (GCNs) are an effective way to learn representations of various graphs. The increasing size and complexity of graphs call for in‐memory computing (IMC) accelerators for GCN to alleviate massive data transmission between off‐chip memory and processing units. However, GCN implementation with IMC is challenging because of the large memory consumption, irregular memory access, and device nonidealities. Herein, a fully binarized GCN (BGCN) accelerator based on computational resistive random‐access memory (RRAM) through software–hardware codesign is presented. The essential operations including aggregation and combination in GCN are implemented on the RRAM crossbar arrays with cooperation between multiply‐and‐accumulation and content‐addressable memory operations. By leveraging the model quantization and IMC on the RRAM, the BGCN accelerator demonstrates less RRAM usage, high robustness to the device variations, high energy efficiency, and comparable classification accuracy compared to the current state‐of‐the‐art GCN accelerators on both graph classification task using the MUTAG and PTC datasets and node classification task using the Cora and CiteSeer datasets. These results provide a promising approach for edge intelligent systems to efficiently process graph‐structured data.

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GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits

Cited by 46 publications

References 18 publications

A customized graph neural network model for guiding analog IC placement

A customized graph neural network model for guiding analog IC placement

Achieving analog layout integrity through learning and migration

Fully Binarized Graph Convolutional Network Accelerator Based on In‐Memory Computing with Resistive Random‐Access Memory

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