Galvanic cell formation: a review of approaches to silicon etching for sensor fabrication

Abstract

A brief review of silicon etching and electrochemistry provides an introduction to galvanic cell formation in silicon/metal contacts in aqueous electrolyte solutions. It is shown that such galvanic cells, which operate under open-circuit conditions, can be used to perform most of the functions of anodic etching and passivation. Applications relevant to sensor fabrication are described. These include the control of surface morphology, etch-stop mechanisms, and microporous and macroporous etching. In addition, surface structuring by open-circuit photoetching, a process which also depends on galvanic effects, is considered.

Self-Assembled Monolayers of Eicosanethiol on Palladium and Their Use in Microcontact Printing

“…80 One of these is to accelerate or localize the etching of a layer. This is the case for the fabrication of porous silicon, microelectro-mechanical systems, or sensors.…”

The stoichiometry of metal assisted etching (MAE) of Si in V2O5+HF and HOOH+HF solutions

“…A metal catalyst can be used to modify the etching process. This was first recognized in a controlled manner by Kelly and co-workers, who coined the term galvanic etching to describe the catalytic etching of silicon induced by planar metal structures [7,8]. Bohn and co-workers [9,10] advanced the range of accessible morphologies by introducing the metal as random or patterned nanoparticles.…”

Optical Properties of Porous Silicon*

“…Kelly and co-workers (Ashruf et al 1999Xia et al 2000;Kelly et al 2001) developed the combination of a metal layer with HF etching in the presence of an oxidant into a more controlled technique by shifting to metals that were not removed from the surface such as Ag, Au, or Pt. Building off of work intended to explain the formation of a galvanic etch stop technique involving etching in alkaline solutions (Ashruf et al 1998) as well as reports of por-Si formation during illumination of Pt coated Si (Zhang et al 1993), they investigated what they called galvanic etching by either connecting the Si wafer to an external metal electrode or by directly depositing the metal on the Si wafer.…”

“…Galvanic etching (Kolasinski 2014c) utilizes a planar metal film and leads to the formation of more or less planar porous silicon films or electropolishing in the vicinity of the metal film depending on the composition of the etchant and ratio of metal surface area to the surface area of the Si exposed to solution. Incorporation of etch stop techniques, for example fabricating p/n junctions by doping and/or epilayer growth, allows for the formation of membranes and freestanding beams (Kelly et al 2001;Sun et al 2012). Becker et al (2010aBecker et al ( , 2011 have optimized galvanic etching to produce films up to ~150 μm thick with specific surface area as high as 900 m 2 /g and pore diameters ~3 nm.…”