GaAs pHEMT Single Pole Double Throw(SPDT) RF Switch Failure Analysis

Shi, Lin; Li, Qiang; Dai, Hongsheng; Wang, Zhida; Jing, Huanqiang

doi:10.1109/ipfa47161.2019.8984831

Cited by 1 publication

(1 citation statement)

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“…One of the attractive processes for RF switch applications is GaAs pHEMT [6][7][8][9][10][11] which dissipates low power, and has low insertion loss (IL), and high power-handling characteristics. Nevertheless, Silicon-on-Insulator (SOI) has become dominant in the design of RF switches [12][13][14][15][16][17][18][19][20][21] recently, due to its capabilities to operate and fabricate at a low supply voltage, as well as to integrate Complementary Metal-Oxide-Semiconductor (CMOS) control logic circuits on chip.…”

Section: Introductionmentioning

confidence: 99%

T/R RF Switch with 150 ns Switching Time and over 100 dBc IMD for Wideband Mobile Applications in Thick Oxide SOI Process

Rikan

Kim

Choi

et al. 2022

Sensors

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This paper presents a fast-switching Transmit/Receive (T/R) Single-Pole-Double-Throw (SPDT) Radio Frequency (RF) switch. Thorough analyses have been conducted to choose the optimum number of stacks, transistor sizes, gate and body voltages, to satisfy the required specifications. This switch applies six stacks of series and shunt transistors as big as 3.9 mm/160 nm and 0.75 mm/160 nm, respectively. A negative charge pump and a voltage booster generate the negative and boosted control voltages to improve the harmonics and to keep Inter-Modulation Distortion (IMD) performance of the switch over 100 dBc. A Low Drop-Out (LDO) regulator limits the boosted voltage in Absolute Maximum Rating (AMR) conditions and improves the switch performance for Process, Voltage and Temperature (PVT) variations. To reduce the size, a dense custom-made capacitor consisting of different types of capacitors has been presented where they have been placed over each other in layout considering the Design Rule Checks (DRC) and applied in negative charge pump, voltage booster and LDO. This switch has been fabricated and tested in a 90 nm Silicon-on-Insulator (SOI) process. The second and third IMD for all specified blockers remain over 100 dBc and the switching time as fast as 150 ns has been achieved. The Insertion Loss (IL) and isolation at 2.7 GHz are −0.17 dB and −33 dB, respectively. This design consumes 145 uA from supply voltage range of 1.65 V to 1.95 V and occupies 440 × 472 µm2 of die area.

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