GaAs MESFET logic with 4-GHz clock rate

The Selectively Doped Heterostructure Transistor: Materials, Devices, and Circuits

“…The use of AND/NOR gates based on dual-gate SDHTs allows much faster circuits than the NOR-gate-only designs, such as a divide-by-two with a delay path of two gates instead of five [108]. Such an AND function can be im-plemented as a dual-gate FET, in which a single source-drain pair encompasses two tandem gates.…”

“…Gated Master-Slave dividers are expected [108] to achieve considerably faster operation than those based on the type-D flip-flop. Nishiuchi et al [130] and Hendel et al [22] have reported performance figures for 0.5and 0.7 μπι gate SDHT master-slave dividers, respectively.…”

Performance prediction for submicron GaAs SDFL logic

“…At liquid nitrogen temperature the delay time was reduced to 17.5 ps with 9.2 mW power dissipation. A 34 ps gate delay has been reported using a depletion mode BFL [ 2 ] , and binary frequency dividers have been operated at around 5 GHz [3,4] Potential superiority of GaAs logic compared to Si is partially related to a higher electron velocity, especially in short submicron devices where the transient ("overshoot" [5-71 or "near-ballistic" [8-121) effects become important. indicate that an electron velocity in excess of 3 x lo5 m/s can be achieved in a submicron GaAs device.…”

“…This precludes the use of common dielectrics such as Sig N 4 , SiQz, and polyimide, which have dielectric constants of less than eight. The two most common candidates for low temperature deposition are TiOz and T a 2 Q j , which can be formed thermally, anodically, or by reactive sputter deposition [3,4] . ed process which produces: a "liftable" integral metal-insulatormetal (MLM) structure, results in the selective deposition of the layers only upon the areas where they are required, and does not expose the other areas of the device wafer to potentially hazardous removal operations.…”

On the scaling of Si-MESFETs

“…The problem of uniformity limits the rninimum channel thickness to about 0. lp in vapor phase epitaxial devices [ 6 ] , while projected ranges of about 450 A have been reported for ion-implanted devices [27]. Fringe capacitances limit the minimum width (W) to about 8 pm in mesa-structured GaAs MESFETs when E = lpm [28]. Lower W, however, has been reported for ion-implanted Si-MESFETs 1291.…”