GaAs DCFL 2.5 Gbps 16-bit Multiplexer/Demultiplexer LSI's

Higashisaka, N.; Shimada, M.; Ohta, Akira; Hosogi, K.; Tobita, Y.; Mitsui, Y.

doi:10.1109/4.303718

Cited by 3 publications

(2 citation statements)

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“…DCFL [24][25][26] is chosen because of its small chip size and power consumption advantages over other GaAs MESFET logic such as SCFL (Source Coupled FET Logic) [29-3 1] and BDCFL (Buffered DCFL) [32]. Power supplies of 0 V (VCC) and -2 V (VSS) are used.…”

Section: L4 Digital Circuitsmentioning

confidence: 99%

“…A completely differential topology is designed to provide sufficient immunity to power supply voltage [20][21][22] and temperature variations [23] in array applications. The differential signal is then fed into the comparator to recover the signal to its full logic swing for the subsequent DCFL [24][25][26] (DirectCoupled FET Logic) digital circuits. The hysteresis control adjusts the amount of hysteresis in the comparator to reduce the effect of noise in the optical receiver.…”

Section: Smart-pixel Designmentioning

confidence: 99%

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<title>64-Gbit/s GaAs integrated DANE receiver/laser driver</title>

Chang

Heins

et al. 1997

SPIE Proceedings

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Optical interconnects provide wide bandwidth, low loss, and high fanout as compared to those for traditional electrical interconnects. In the past years many high performance optoelectronic circuits have been demonstrated. However, most of them require complicated process and exotic devices. To make optical interconnects in real system and commercial use, circuits utilizing manufacturable, robust, and low-cost technology have to be realized. Ion implanted GaAs MESFETs provide great promise due to their simplicity in manufacturing and their high speed performance. The optical characteristics of GaAs materials also make this technology favorable in realizing low-cost, high-performance OEICs (Opto-Electronic Integrated Circuits).Based on the experience obtained in the successful implementation of the 10 GHz receivers [1] and motivated by the increasing demand for highly parallel optical interconnects, high-performance two-dimensional 4x4 and 8x8 smart-pixel arrays capable of detect, amplify, negate, and emit ( DANE) optical signals utilizing Vitesse's HGaAs-III 0.6 im E/D MESFET process have been developed. The main design goals are aggregated data rates of 16 and 64 Gb/s (at 1 Gb/s/channel for 4x4 and 8x8 arrays), power consumption of less than 100 mW/channel, and sensitivity of better than -20 dBm. To make the data transmission transparent, fully dc-coupled circuits are designed. Obstacles in array implementation are also overcame, by the novel design of the fully differential optical receivers. Approximately 5,000 and 20,000 active devices are integrated in the 4x4 and 8x8 arrays, respectively. The simulated results of the complete circuits show that the design goals of low power, high speed, high density, high sensitivity, high process and power supply tolerance are met.

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Section: L4 Digital Circuitsmentioning

confidence: 99%