Future Aspects of MOCVD Technology for Epitaxial Growth of Semiconductors

Detchprohm, Theeradetch; Ryou, Jae‐Hyun; Li, Xiaohang; Dupuis, R. D.

doi:10.1002/9781119313021.ch14

Cited by 4 publications

(3 citation statements)

References 195 publications

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“…The possible simplified experimental processing steps are listed in figure 3(c) based on recent demonstrations in nanowire geometries [30][31][32][33][34][35]. It is known that the atomic layer deposition (ALD) is advanced to deposit layer by layer of HfO 2 [37].…”

Section: Design and Working Principle Of Omfs-vtfetmentioning

confidence: 99%

“…(iii) Doped source (p ++ ), (iv) channel (p), and (v) drain (n + ) regions through ion implantation. (vi) Epitaxy growth (Si) and selective ndopant by metalorganic vapour-phase epitaxy (MOCVD) [32], (vii) oxide and (viii) ferroelectric layer by atomic layer deposition (ALD) and or pulsed layer deposition (PLD) [33], and (ix) TiN deposition and utilizing isotropic etching for GAA geometry [34,35]. ).…”

Section: Design and Working Principle Of Omfs-vtfetmentioning

confidence: 99%

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Gate‐all‐around nanowire vertical tunneling FETs by ferroelectric internal voltage amplification

Thoti

2021

Nanotechnology

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This work illustrates the most effective way of utilizing the ferroelectricity for tunneling field-effect transistors (TFETs). The ferroelectric (Hf0.5Zr0.5O2) in shunt with gate-dielectric is utilized as an optimized metal–ferroelectric–semiconductor (OMFS) option to improve the internal voltage (V int ) for ample utilization of polarization and electric fields of Hf0.5Zr0.5O2 across the tunneling region. The modeling of V int signifies 0.15–1.2 nm reduction in tunneling length (λ) than the nominal metal–ferroelectric–insulator–semiconductor (MFIS) option. Furthermore, the TFET geometry with the scaled-epitaxy region as vertical TFET (VTFET), strained Si0.6Ge0.4 as source, and gate-all-around nanowire options are used as an added advantage for further enhancement of TFET’s performance. As a result, the proposed design (OMFS-VTFET) achieves superior DC and RF performances than the MFIS option of TFET. The figure of merits in terms of DC characteristics in the proposed and optimized structure are of improved on-current (=0.23 mA μm−1), high on-to-off current ratio (=1011), steep subthreshold swing (=33.36 mV dec−1), and superior unity gain cut-off frequency (≥300 GHz). The design is revealed as energy-efficient with significant reduction of energy-efficiency in both logic and memory applications.

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Section: Design and Working Principle Of Omfs-vtfetmentioning

confidence: 99%

Section: Design and Working Principle Of Omfs-vtfetmentioning

confidence: 99%

Gate‐all‐around nanowire vertical tunneling FETs by ferroelectric internal voltage amplification

Thoti

2021

Nanotechnology

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“…More details on the calibration procedure and the process flow of the proposed structure can be found from the supplementary file and our recent works (see the supplementary file). [12][13][14][15][16][17] The design of the proposed CTFET is equipped with conventional tunneling options (point-tunneling) similar to the experimental work. 10) Hence, the working principle of the CTFET is based on source (S)-channel (Ch) tunneling in both p-and n-CTFET devices as electron and hole BTBT due to the point-electric field (E).…”

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confidence: 99%

Design and exploration of vertically stacked complementary tunneling field-effect transistors

Thoti,

2023

Appl. Phys. Express

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The purpose of this letter is to design and explore vertically stacked complementary tunneling field effect transistors (CTFETs) using complementary field effect transistor (CFET) technology for emerging technology nodes. As a prior work, the CTFET’s device level simulations are implemented and deliberated in strict compliance with the experimental demonstration requirements. This work comprises physical and DC characteristic examination by scaling the footprint (FP), which refers to the separation between p- to n-CTFET (Dpn). By utilizing the 50% reduction of FP, the work is extended to CTFET-6T SRAM demonstration and characterization with hold/read noise margin analysis.

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First-principle calculations to investigate structural, electronic, mechanical, optical, and thermodynamic features of promising (La, In)-doped AlSb for optoelectronic applications

Moin,

Anwar,

Ahmad

et al. 2023

J Mol Model

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Future Aspects of MOCVD Technology for Epitaxial Growth of Semiconductors

Cited by 4 publications

References 195 publications

Gate‐all‐around nanowire vertical tunneling FETs by ferroelectric internal voltage amplification

Gate‐all‐around nanowire vertical tunneling FETs by ferroelectric internal voltage amplification

Design and exploration of vertically stacked complementary tunneling field-effect transistors

First-principle calculations to investigate structural, electronic, mechanical, optical, and thermodynamic features of promising (La, In)-doped AlSb for optoelectronic applications

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