Design and exploration of vertically stacked complementary tunneling field-effect transistors

Abstract

The purpose of this letter is to design and explore vertically stacked complementary tunneling field effect transistors (CTFETs) using complementary field effect transistor (CFET) technology for emerging technology nodes. As a prior work, the CTFET’s device level simulations are implemented and deliberated in strict compliance with the experimental demonstration requirements. This work comprises physical and DC characteristic examination by scaling the footprint (FP), which refers to the separation between p- to n-CTFET (Dpn). By utilizing the 50% reduction of FP, the work is extended to CTFET-6T SRAM demonstration and characterization with hold/read noise margin analysis.