Functional Test Generation for Digital Circuits Described Using Binary Decision Diagrams

Abadir,; Reghbati,

doi:10.1109/tc.1986.1676774

Cited by 29 publications

(9 citation statements)

References 15 publications

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“…The overall results of the case study were quite promising and we are convinced that our approach is a viable and effective way for generating tests for LSI circuits [12,13,14,15]. We believe that the test generation procedure and the test simplification technique can both be automated without much difficulty.…”

Section: Vll Summarymentioning

confidence: 83%

Test Generation for LSI: A Case Study

Abadir¹,

Reghbati²

1984

21st Design Automation Conference Proceedings

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A new automatic test generation approach for LSl circuits has been presented in the companion papers [1,2]. In this paper we generate tests for a typical LSI circuit using the new approach. The goal of this study is to gain insight into the problems involved in using the test generation procedures.A formal model C for a 1-bit microprocessor slice is defined which has all the main features of commercially available bit slices such as the Am2901.The circuit C is modeled as a network of interconnected functional modules.The functions of the individual modules are described using binary decision diagrams, or equivalently using experiments derived from the diagrams.Using our test generation technique, we derive tests for the circuit C capable of detecting various faults covered by our fault model [I]. It is shown that backtracking is rarely needed while generating tests for C. Also, we show that generating a multiple vector test is not required for any of the faults considered in the study.The length of the circuit's test sequence is significantly reduced using the fault collapsing method.A discussion of how to model some of the features of LSI circuits that are not included in the circuit C is presented.A comparison between the length of the test generated by our method and other manually-generated ones is also presented. INDEX TERMS

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Section: Vll Summarymentioning

confidence: 83%

Test Generation for LSI: A Case Study

Abadir¹,

Reghbati²

1984

21st Design Automation Conference Proceedings

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“…Binary decision diagrams (BDD's) [2], [9] have been used for synthesizing and analyzing combinational as well as sequential circuits [1], [4], [5], [7], [8], [15]. We have shown [11] that BDD's are not well suited for synthesizing area-efficient PTL networks.…”

Section: A Backgroundmentioning

confidence: 99%

“…• Each node in the 123-DD has a unique number as its Node_id. 1 It will be clear later that we use the term edge when the edge connects exactly two nodes and the term hyperedge for situations where m (m >=2) nodes are connected. • If two or more nonterminal nodes are connected by a dashed line, the dashed line represents a hyperedge and denotes the fact that the corresponding nodes are connected by a metal line.…”

Section: B 123-decision Diagram Modelmentioning

confidence: 99%

Design of dynamic pass-transistor logic circuits using 123 decision diagrams

Jaekel

Bandyopadhyay

Jullien

1998

IEEE Trans. Circuits Syst. I

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Pass transistor logic (PTL) has advantages over standard CMOS designs in terms of layout density, circuit delay, and power consumption and is well suited for pipelined circuits. In this paper we develop a decision-diagram-based model, the 123-decision diagram, which can be used to efficiently synthesize PTL circuits, and we investigate multilevel logic synthesis techniques for complex, pipelined PTL networks using this model. Experiments on a large number of benchmark circuits show that PTL networks synthesized using our techniques are significantly more economic in terms of silicon area compared to those using existing techniques.

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“…Binary Decision Diagrams (BDDs) [1]- [3] are a well established data structure for this purpose. BDDs are employed in many EDA applications, such as digital circuits synthesis [4], verification [5], testing [6], simulation [7], and others. Original BDDs are driven by the Shannon's expansion to decompose a Boolean function until the constant logic values are encountered.…”

Section: Introductionmentioning

confidence: 99%

An efficient manipulation package for Biconditional Binary Decision Diagrams

Amarù¹,

Gaillardon²,

Micheli³

2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

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Abstract-Biconditional Binary Decision Diagrams (BBDDs) are a novel class of binary decision diagrams where the branching condition, and its associated logic expansion, is biconditional on two variables. Reduced and ordered BBDDs are remarkably compact and unique for a given Boolean function. In order to exploit BBDDs in Electronic Design Automation (EDA) applications, efficient manipulation algorithms must be developed and integrated in a software package. In this paper, we present the theory for efficient BBDD manipulation and its practical software implementation. The key features of the proposed approach are (i) strong canonical form pre-conditioning of stored BBDD nodes, (ii) recursive formulation of Boolean operations in terms of biconditional expansions, (iii) performance-oriented memory management and (iv) dedicated BBDD re-ordering techniques. Experimental results show that the developed BBDD package achieves an average node count reduction of 19.48% and a speed-up factor of 1.63x with respect to a state-of-art decision diagram manipulation package. Employed in the synthesis of datapath circuits, the BBDD manipulation package is capable to advantageously restructure arithmetic operations producing 11.02% smaller and 32.29% faster circuits as compared to a commercial synthesis flow.

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Functional Test Generation for Digital Circuits Described Using Binary Decision Diagrams

Cited by 29 publications

References 15 publications

Test Generation for LSI: A Case Study

Test Generation for LSI: A Case Study

Design of dynamic pass-transistor logic circuits using 123 decision diagrams

An efficient manipulation package for Biconditional Binary Decision Diagrams

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