Design of dynamic pass-transistor logic circuits using 123 decision diagrams

Jaekel, Arunita; Bandyopadhyay, Subir; Jullien, G.A.

doi:10.1109/81.735439

Cited by 13 publications

(5 citation statements)

References 34 publications

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“…In [20] a method named 123dd has been presented in which the improvement of the number of transistors in DCVS tree for: F = (1011 0000 1011 0011 1011 1001 1011 0001) is more than 15% (from 26tT to 22T). If we implement F with the new proposed algorithm we will only need 16T.…”

Section: Resultsmentioning

confidence: 99%

Minimization of Multiple-Valued Decision Diagrams Based on Matrix Computation

Kavehie¹,

Navi²,

Afjei³

et al. 2008

American J. of Applied Sciences

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This paper proposes a new algorithm to simplify the multiple valued logic (MVL) decision diagrams. This algorithm is based on a new level coupling rule. By changing the designer's perspective towards the design, this rule can make further simplification possible. In most of state of the art designs, the decision diagram plays a serious role in the implementation of the logical functions. The proposed algorithm uses the new level coupling rule and combines it with the existing ones, presenting a new method in simplifying and implementing the basic decision diagram.

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Section: Resultsmentioning

confidence: 99%

Minimization of Multiple-Valued Decision Diagrams Based on Matrix Computation

Kavehie¹,

Navi²,

Afjei³

et al. 2008

American J. of Applied Sciences

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“…The detail of this method is explained in [6] and [7]. Each 123dd has a number of non-terminal nodes which are shown as a circle.…”

Section: Dd Methodsmentioning

confidence: 99%

Pull Down Network Minimization, Based on Equivalent Functions Concept, in DCVS Circuit Design

Mohtashami

Navi

Mahini

et al. 2007

2007 14th International Conference on Mixed Design of Integrated Circuits and Systems

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In this paper, a novel method with well defined algorithm is applied for constructing optimized DCVS circuits for a Boolean function. In this approach different methods of designing are studied carefully and compared with each other; afterwards a method which can produce fast, low power, low cost DCVS structures from random Boolean functions is demonstrated. The distinction of this approach despite the others is that it is not heuristic; the designer does not interfere with details and also with no intelligence can create the optimized DCVS circuit from a defined Boolean function.

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“…Figure 10 shows a circuit diagram of the proposed fulladder based on the novel compound logic. The logic is combined of a conventional CMOS logic and passtransistor logic [9,10]. The compound logic only selects both the advantage of driving capability in CMOS logic and the advantage of simple switch connection in passtransistor logic.…”

Section: Leaf-cell Based Layoutmentioning

confidence: 99%

Design Methodology of a 32‐bit Arithmetic Logic Unit with an Adaptive Leaf‐cell Based Layout Technique

Cho

Song

2000

VLSI Design

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In general, an arithmetic logic unit (ALU) of a DSP core is composed of an adder, multiplier and shifter. In order to obtain a high-performance 32-bit ALU, in this paper, an adaptive leaf-cell based layout technique is proposed. Thus novel architectures of 64-bit adder, 32 × 32-bit multiplier, and 32-bit shifter are proposed. The architecture of the proposed 64-bit adder is based on the conditional select addition with regular adaptive multiplexers. Secondly, novel optimized data compressors with a compound logic are proposed in a 32 × 32-bit multiplier. Finally, a shift algorithm with a pre-mask decoder is proposed for the 32-bit barrel shifter. They have been fabricated with 0.25 μm 1-poly 5-metal CMOS process, and we have obtained desired experimental results.

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Design of dynamic pass-transistor logic circuits using 123 decision diagrams

Cited by 13 publications

References 34 publications

Minimization of Multiple-Valued Decision Diagrams Based on Matrix Computation

Minimization of Multiple-Valued Decision Diagrams Based on Matrix Computation

Pull Down Network Minimization, Based on Equivalent Functions Concept, in DCVS Circuit Design

Design Methodology of a 32‐bit Arithmetic Logic Unit with an Adaptive Leaf‐cell Based Layout Technique

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