Functional Built-In Self-Test for processor cores in SoC

Abstract

A methodology for organization of at-speed functional Built-In Self-Test in processors, based on real functional routines is presented. The proposed self-test includes on-chip test application and response collection by using the functionality of the processor under test. We use divide-and-conquer approach. At component level, tests are targeting faults in components. At processor level, the functionality of the processor is used to apply functional test patterns to each component at-speed.Differently from usual Built-in Self-Test schemes, the test patterns are not needed to store in the chip under test, they will be generated on-line by the resources of the system.

Comparison of two approaches to improve functional BIST fault coverage

“…In the case of using the HyBIST approach we introduce a set of multiplexers at the input of ALU to have the possibility of selecting the source of test patterns, either using the normal working mode, or using the stored in the memory additional deterministic test patterns, as shown in Fig.2 [26]. The HyBIST test session in Fig.2 is carried out in two parts: first, a micro-program selected to exercise the data path in a functional working mode, and second, a sequence of test patterns generated in a deterministic way.…”

“…The HyBIST test session in Fig.2 is carried out in two parts: first, a micro-program selected to exercise the data path in a functional working mode, and second, a sequence of test patterns generated in a deterministic way. In this paper, the target will be not to find a tradeoff between the lengths of the functional and deterministic parts of the test, like in [26], rather to find the number of needed deterministic patterns at the given fault coverage of the functional part of the test…”