Comparison of two approaches to improve functional BIST fault coverage

Abstract

Two approaches to improve the fault coverage of functional logic BIST in digital circuits are proposed and investigated. The first approach is based on introducing of additional test points. An experimental tool set is developed for fast evaluation of the number of control points that is needed to achieve 100% fault coverage for the given functional test sequence. A novel algorithm is proposed to minimize the number of control points. The second approach is based on complementing the functional test with additional deterministic test patterns. The pros and cons of both approaches are highlighted and discussed.

A tool set for teaching design-for-testability of digital circuits

“…To minimize the number of control points we apply the method described in [11]. By fault simulation of the given sequence of test patterns T we will determine the subsets of nodes S(k) in the circuit, where k means that for each node s∈S(k) the fault at this node is detected k or less times during the test T. If k = 0 then the fault is undetectable by T. If k > 0, but still very small, then the probability of testing the faults at the output branches of the gate is expected to be the smaller, the smaller is k. This consideration suggests to include into the set of candidate nodes for insertion of control points not only the nodes of S(0), but all the nodes of S(k*) where the value of k* can be predetermined.…”