Fully parallel comparator for the moduli set {2n,2n-1,2n+1}

Eivazi, Shiva Taghipour; Hosseinzadeh, Mehdi; Mirmotahari, Omid

doi:10.1587/elex.8.897

Cited by 7 publications

(6 citation statements)

References 3 publications

(4 reference statements)

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“…From the above analysis, it can be concluded that the proposed comparator has less latency than that in [3,4]. The proposed comparator has a very significant delay reduction.…”

Section: Comparison and Analysismentioning

confidence: 77%

“…Based on the simple gate-count and gate-delay model used in [3,4], the performance comparison can be listed as: Unit Gate Delay: [3]: 4n þ log n þ 36 [4]: 2n þ 39 Proposed: 6 log n þ 26 Unit Gate Area: [3]: 115n þ 186 [4]: 132n þ 55…”

Section: Comparison and Analysismentioning

confidence: 99%

“…obtain delay savings of about 8%-25% with an average area saving of 32% against the reference comparators in [4]. Compared with the reference comparators in [3], the synthesized results demonstrate that the proposed comparators need less latency and area overhead.…”

mentioning

confidence: 93%

“…The authors of [3] presented a RNS comparison technique, which performs comparison without using a redundant module and complete converting from RNS to binary systems. The authors of [4] proposed the comparison technique based on sign detection.…”

Section: Introductionmentioning

confidence: 99%

“…Compared with the reference comparators in [4], the proposed comparators compare two residues in RNS by subtracting and converting the final result to binary for comparison, reducing two converting logics in the reference comparators in [4] into one converting logic. Based on the new presentation, the proposed architecture is more efficient that in [4], which is shown in the synthesized results.…”

mentioning

confidence: 99%

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High Speed Comparator for the Moduli {2n, 2n-1, 2n+1}

Zhao

et al. 2013

IEICE Electron. Express

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f2 n ; 2 n À 1; 2 n þ 1g is one of the most commonly used moduli in residue number systems. In this express, we propose a novel comparator for the moduli f2 n ; 2 n À 1; 2 n þ 1g. Based on the proposed architecture, we can design high speed comparator for the moduli f2 n ; 2 n À 1; 2 n þ 1g, which is the fastest among all known comparators for the moduli f2 n ; 2 n À 1; 2 n þ 1g. The performance of the proposed comparator is evaluated and compared with the earlier fast comparators for the moduli f2 n ; 2 n À 1; 2 n þ 1g, based on a simple gate-count and gate-delay model. The proposed comparator can improve the state-of-art by 8% on the average in terms of area and 6% on the average in terms of performance delay.

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“…From the above analysis, it can be concluded that the proposed comparator has less latency than that in [3,4]. The proposed comparator has a very significant delay reduction.…”

Section: Comparison and Analysismentioning

confidence: 77%

Section: Comparison and Analysismentioning

confidence: 99%

mentioning

confidence: 93%

Section: Introductionmentioning

confidence: 99%

mentioning

confidence: 99%

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High Speed Comparator for the Moduli {2n, 2n-1, 2n+1}

Zhao

et al. 2013

IEICE Electron. Express

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Scaling, Base Extension, Sign Detection and Comparison in RNS

Mohan¹

2016

Residue Number Systems

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Sign Detection and Number Comparison on RNS 3-Moduli Sets $$\{2^n-1, 2^{n+x}, 2^n+1\}$$ { 2 n - 1 , 2 n + x , 2 n + 1 }

Sousa

Martins

2016

Circuits Syst Signal Process

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Number comparison, sign identification and overflow detection are important operations, especially for digital signal processing, but hard to perform using the residue number system (RNS). In this paper, a new method is proposed for sign identification and number comparison based on an optimized version of the mixed radix conversion for the augmented 3-moduli sets {2 n + 1, 2 n − 1, 2 n+x }(0 ≤ x ≤ n). Notably, most of the computations are directly performed on the moduli channels, thus allowing to easily adapt this new method to any RNS processor. Accordingly, this paper proposes an efficient unified very large scale integration architecture based on the presented methodology, which can be used not only to design application specific integrated circuits (ASICs) but also to configure field-programmable gate arrays (FPGAs). The implementation results that were obtained using 65 nm CMOS technologies show that the proposed architecture provided comparators that are more efficient than the related state of the art, by considering as a figure of merit the area time product. More specifically, the considered ASIC and FPGA implementations provide relative improvements in the efficiency of up to 57 and 38 %, respectively. The experimental assessment also shows that the power consumption of the proposed This work was supported by national funds through FCT (Fundação para a Ciência e a Tecnologia) under project UID/CEC/50021/2013 and by the Ph.D. Grant with reference SFRH/BD/103791/2014. Electronic supplementary material The online version of this article (Circuits Syst Signal Process circuits is significantly lower than the related state of the art, with relative reductions of up to 50 %.

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Fully parallel comparator for the moduli set {2n,2n-1,2n+1}

Cited by 7 publications

References 3 publications

High Speed Comparator for the Moduli {2<sup><i>n</i></sup>, 2<sup><i>n</i></sup>-1, 2<sup><i>n</i></sup>+1}

High Speed Comparator for the Moduli {2<sup><i>n</i></sup>, 2<sup><i>n</i></sup>-1, 2<sup><i>n</i></sup>+1}

Scaling, Base Extension, Sign Detection and Comparison in RNS

Sign Detection and Number Comparison on RNS 3-Moduli Sets $$\{2^n-1, 2^{n+x}, 2^n+1\}$$ { 2 n - 1 , 2 n + x , 2 n + 1 }

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