Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond

Khakifirooz, A.; Cheng, K.; Jagannathan, B.; Kulkarni, P.; Sleight, J.W.; Shahrjerdi, Davood; Chang, Josephine; Lee, Sung Jae; Li, Junjun; Bu, H.; Gauthier, Robert; Doris, B.; Shahidi, G.

doi:10.1109/isscc.2010.5434014

Cited by 33 publications

(15 citation statements)

References 3 publications

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“…Also, sub-threshold slopes are expected to improve, helping to allow lower device threshold voltages which in turn will facilitate lower voltage operation. For those designers already designing in SOI, history effects are expected to disappear as the body becomes fully depleted [21].…”

Section: New Fully-depleted Devicesmentioning

confidence: 99%

Circuit design challenges at the 14nm technology node

Warnock¹

2011

Proceedings of the 48th Design Automation Conference

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Technology scaling non-idealities, already apparent in the transitions between previous technology generations, will become even more pronounced as the world moves from the 22nm node to the 14nm node. Digital logic designers working on highperformance microprocessors and similar projects will face significant new challenges as the basic FET structure is changed in a fundamental way, in order to squeeze more performance from scaled devices. New design constraints and new sources of variability will have to be understood, and new methodologies will be required to enable robust, high-speed designs. In addition, the metal interconnects between devices will also be stressed. Scaled wire RC will likely increase, and new tools and methods will be needed to ensure reliable designs.

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Section: New Fully-depleted Devicesmentioning

confidence: 99%

Circuit design challenges at the 14nm technology node

Warnock¹

2011

Proceedings of the 48th Design Automation Conference

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“…The first option has the cost advantage as all devices are fabricated on ETSOI layer while the second option has design advantage as the conventional bulk design IP can readily be readily ported to ETSOI SoC. We have successfully demonstrated all-ETSOI integration [2][3][4]. Multi-Vt ETSOI transistors can be achieved by two complementary approaches: (1) gate workfunction engineering by adopting various workfunction tuning layers [4] and (2) back gating/bias by doping/applying voltage under the BOX [5].…”

Section: Etsoi Soc Design and Integrationmentioning

confidence: 99%

“…Another major advantage of ETSOI is the low device variability, thanks to the undoped ETSOI channel which eliminates the random dopant fluctuation, a major source of device variation. We have demonstrated a record low ETSOI variability which renders SRAM operated at much reduced voltages while maintaining good static noise margin (SNM) [2][3]. Fig.…”

Section: Etsoi Device Performancesmentioning

confidence: 99%

“…Extremely thin SOI (ETSOI) has been recognized as a viable device architecture for continued CMOS scaling to 20nm node and beyond owing to following advantages: superior shortchannel control, undoped channel and thus inherent low device variability, no history effect, planar structure easing device fabrication, seamless design migration from bulk planar technology, and unique back gate opportunities for tuning device characteristics and power management [1][2][3][4][5]. In this paper, we provide an overview on the current status of ETSOI for systemon-chip (SoC) application based on our recent work [2][3][4].…”

Section: Introductionmentioning

confidence: 99%

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Extremely Thin SOI (ETSOI) - a Planar CMOS Technology for System-on-chip Applications

Cheng¹,

Khakifirooz²,

Kulkarni³

et al. 2011

Extended Abstracts of the 2011 International Conference on Solid State Devices and Materials

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“…">IntroductionRaised S/D (RSD) epitaxy provides a significant knob to meet the short-channel and leakage requirements of highly scaled MOS devices [1]. In more recent planar technologies using thin-body devices, faceted RSD epitaxy was presented as a key process that enables performance, overcoming major device issues such as doping control and parasitic capacitance [2] [3]. However, as device physical dimensions continue to scale, faceted RSD epitaxy integration presents new challenges in term of loading effects, facet reproducibility and control.…”

mentioning

confidence: 99%

Raised S/D for Advanced Planar MOSFET devices: Challenges and Applications for the 20nm Node and Beyond

Loubet¹,

Khare²,

Mehta³

et al. 2010

Extended Abstracts of the 2010 International Conference on Solid State Devices and Materials

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IntroductionRaised S/D (RSD) epitaxy provides a significant knob to meet the short-channel and leakage requirements of highly scaled MOS devices [1]. In more recent planar technologies using thin-body devices, faceted RSD epitaxy was presented as a key process that enables performance, overcoming major device issues such as doping control and parasitic capacitance [2] [3]. However, as device physical dimensions continue to scale, faceted RSD epitaxy integration presents new challenges in term of loading effects, facet reproducibility and control. In this paper, the feasibility and integration of flat and faceted RSD silicon epitaxy are investigated. As a function of process conditions, different facet features can be generated. The ability of cyclic deposition to achieve either flat or faceted RSD epitaxy at low temperature with a very good repeatability will be discussed. Finally, the pitch dependence of the faceted cyclic epitaxy will be highlighted and the extendibility of this technique to the 20nm node and further will be addressed. ExperimentsAll RSD epitaxy experiments were carried out using an industrially available Applied Materials 300mm-wafer RT-CVD reactor starting from patterned SOI wafers featuring thin 8nm silicon channel and 6nm SiN spacers (figure 1). These test wafers were patterned using the 20nm design ground rules with different gate pitches and as well as large 100µmx100µm isolated areas on the same wafer. Regarding the process conditions, a low total pressure of 20Torr was used in all these experiments to ensure minimized loading effects with a standard chlorinated DCS/HCl gas mixture and H 2 as carrier gas. The RSD morphology obtained after both standard and cyclic epitaxy next to SiN spacers will be compared for different process conditions. Controlling the HCl concentration or exposure time at a given concentration enables us to generate two distinct RSD profiles: a conventional flat shape showing epitaxial growth along [100] direction or a faceted RSD epitaxy featuring both (111) and (311) facets next to SiN spacers. Results and Discussions RSD using standard DCS/HCl/H 2 gas mixture:First, we will consider the different RSD epitaxy shapes that can be generated with a standard chlorinated chemistry using direct injection of DCS/HCl. The temperature range of 750°C -800°C was studied at constant DCS mass flow but various HCl concentrations. The impact of the HCl partial pressure is presented in figures 2a and 2b. As the DCS/HCl ratio is decreased from 1.2 to 1 at 800°C, epitaxy shape is modified from flat to faceted. Indeed, HCl gas is the main parameter which controls the facet extension and faceted epitaxy can be obtained in a wide range of temperatures, as highlighted in figures 2b and 2c. With a standard epitaxy, only the (311) facet was observed next to SiN spacers and at a fixed growth rate, the extension of this particular plane becomes less pronounced when the temperature is lowered as the ratio r 311 =GR (311) /GR (100) increases [4]. Therefore, only a flat epitaxy delimited by th...

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Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond

Cited by 33 publications

References 3 publications

Circuit design challenges at the 14nm technology node

Circuit design challenges at the 14nm technology node

Extremely Thin SOI (ETSOI) - a Planar CMOS Technology for System-on-chip Applications

Raised S/D for Advanced Planar MOSFET devices: Challenges and Applications for the 20nm Node and Beyond

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