Fully 3-Dimensional NOR Flash Cell with Recessed Channel and Cylindrical Floating Gate - A Scaling Direction for 65nm and Beyond

Sim, Sung‐Han; Kim, Kwang S.; Lee, Heon Kyu; Han, Jung In; Kwon, Wook Hyim; Han, Jee Hoon; Lee, Bong Yong; Jung, Cheol; Park, Jeung Hwan; Kim, Dae Joung; Jang, Dae Hyun; Lee, W.H.; Park, Chan-Kwang; Kim, Kinam

doi:10.1109/vlsit.2006.1705195

Cited by 9 publications

(7 citation statements)

References 1 publication

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“…Device scaling is very effective for the fabrication of high-density and low-cost flash memories. However, further scaling of conventional bulk planar MOSFET type flash memories becomes very difficult because of the increased short-channel effect (SCE) and the lowered source-drain (SD) breakdown voltage (BV DS ) with scaling down device size [1][2][3]. Especially, in the NOR-type flash memory, further scaling of device size faces the theoretical limit of BV DS which corresponds to the silicon (Si) and silicon dioxide (SiO 2 ) conduction band difference (3.2 eV).…”

Section: Introductionmentioning

confidence: 99%

“…Especially, in the NOR-type flash memory, further scaling of device size faces the theoretical limit of BV DS which corresponds to the silicon (Si) and silicon dioxide (SiO 2 ) conduction band difference (3.2 eV). This indicates that channel hot electron (CHE) programming cannot be guaranteed in the scaled NOR-type flash memories with gate length (L g ) smaller than 100 nm [2,3]. On the other hand, three-dimensional (3D) channel devices, such as fin-type double-gate (DG) MOSFET (FinFET) and fin-channel tri-gate (TG) device, provide excellent SCE immunity owing to the strong controllability of channel potential by the multiple gates [4][5][6][7][8][9][10][11][12][13].…”

Section: Introductionmentioning

confidence: 99%

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Comparative Study of Charge Trapping Type SOI-FinFET Flash Memories with Different Blocking Layer Materials

Liu

Nabatame

Matsukawa

et al. 2014

JLPEA

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The scaled charge trapping (CT) type silicon on insulator (SOI) FinFET flash memories with different blocking layer materials of Al 2 O 3 and SiO 2 have successfully been fabricated, and their electrical characteristics including short-channel effect (SCE) immunity, threshold voltage (V t ) variability, and the memory characteristics have been comparatively investigated. It was experimentally found that the better SCE immunity and a larger memory window are obtained by introducing a high-k Al 2 O 3 blocking layer instead of a SiO 2 blocking layer. It was also confirmed that the variability of V t before and after one program/erase (P/E) cycle is almost independent of the blocking layer materials. . Low Power Electron. Appl. 2014, 4 154 OPEN ACCESS J

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Comparative Study of Charge Trapping Type SOI-FinFET Flash Memories with Different Blocking Layer Materials

Liu

Nabatame

Matsukawa

et al. 2014

JLPEA

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“…SRAM memories are used to store the variables while NVM is used to store the instruction code. Embedded NVM are based on NOR flash technologies [5] [6] [7] down to 40nm commercial CMOS technologies. For both server applications (standalone NVM) and autonomous connected nodes (embedded NVM), scaling down the technology nodes is a real struggle.…”

Section: Communication Cost Between Processing Units and Memories Anmentioning

confidence: 99%

Design and Simulation of a 128 kb Embedded Nonvolatile Memory Based on a Hybrid RRAM (HfO2 )/28 nm FDSOI CMOS Technology

Portal

Bocquet

Onkaraiah

et al. 2017

IEEE Trans. Nanotechnology

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Emerging Non-Volatile Memories (NVM) based on resistive switching mechanism such as RRAM are under intense R&D investigation by both academics and industries. They provide high write/read speed, low power and good endurance (e.g. >10 12) beyond mainstream NVMs, enabling them to be a good candidate for Flash replacement in Micro-Controller Unit (MCU). This replacement could significantly decrease the power consumption and the integration cost on advanced CMOS nodes. This paper presents firstly the HfO 2 based RRAM technology and the associated compact model, which includes related physics and model card fitting experimental electrical characterizations. The 128kb memory architecture based on RRAM technology and 28nm FDSOI CMOS core process is presented with a bottom-up approach, starting from the bit-cell definition up to the complete memory architecture implementation. The key points of the architecture are the use of standard logic MOS exclusively, avoiding any high voltage MOS usage, program/verify procedure to mitigate cycle to cycle (C2C) variability issue and direct bitcell read access for characterization purpose. The proposed architecture is validated using post-layout simulations on MOS and RRAM corner cases.

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“…In some research [1][2][3][4][5], high-K materials are used as O/N/O layers to decrease E ot . In addition, some new structures have been proposed to suppress SCEs of flash memory, and thus can improve the flash cell scaling capability [6][7][8]. As an alternative, a recessed channel device has been used in DRAM [9] and flash applications [8,10], due to its suppression of leakage current and its lengthened effective gate length.…”

Section: Introductionmentioning

confidence: 99%

“…In addition, some new structures have been proposed to suppress SCEs of flash memory, and thus can improve the flash cell scaling capability [6][7][8]. As an alternative, a recessed channel device has been used in DRAM [9] and flash applications [8,10], due to its suppression of leakage current and its lengthened effective gate length. However, the P/E voltage cannot be reduced much from these structures.…”

Section: Introductionmentioning

confidence: 99%

A low-voltage flash memory cell utilizing the gate-injection program/erase method with a recessed channel structure

Wu¹,

Huang²,

Wang³

et al. 2008

Semicond. Sci. Technol.

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In this paper, a low-voltage recessed channel SONOS flash memory using the gate-injection program/erase method is proposed and investigated for NAND application. It is shown that the proposed flash memory can achieve 8 V lower programming voltage compared with planar flash memory, due to the effective capacitance coupling and the electric-field enhancement by combining the recessed channel structure and the gate-injection program/erase method. In addition, more than 30% larger threshold voltage window and improved short channel effects can be obtained in the proposed flash memory.

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Fully 3-Dimensional NOR Flash Cell with Recessed Channel and Cylindrical Floating Gate - A Scaling Direction for 65nm and Beyond

Cited by 9 publications

References 1 publication

Comparative Study of Charge Trapping Type SOI-FinFET Flash Memories with Different Blocking Layer Materials

Comparative Study of Charge Trapping Type SOI-FinFET Flash Memories with Different Blocking Layer Materials

Design and Simulation of a 128 kb Embedded Nonvolatile Memory Based on a Hybrid RRAM (HfO2 )/28 nm FDSOI CMOS Technology

A low-voltage flash memory cell utilizing the gate-injection program/erase method with a recessed channel structure

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