A low-voltage flash memory cell utilizing the gate-injection program/erase method with a recessed channel structure

Abstract

In this paper, a low-voltage recessed channel SONOS flash memory using the gate-injection program/erase method is proposed and investigated for NAND application. It is shown that the proposed flash memory can achieve 8 V lower programming voltage compared with planar flash memory, due to the effective capacitance coupling and the electric-field enhancement by combining the recessed channel structure and the gate-injection program/erase method. In addition, more than 30% larger threshold voltage window and improved short channel effects can be obtained in the proposed flash memory.

A control-gate-assisted erasing method for a single-poly EEPROM cell with metallic control gate structure

“…Recently, low cost has been an important consideration in nonvolatile memory (NVM) application. In addition, the demands of the embedded nonvolatile memory for system integration on a chip is rapidly increasing, Among the various NVM memory structures [1][2][3][4][5][6], single-poly memory is one of the promising solutions for low-cost-embedded NVM applications [6][7][8][9][10][11][12]. The conventional single-poly EEPROM cells with diffused n-well CG suffer some issues, such as the large CG junction capacitance and resistance, the reduction of the coupling factor (α CG ), and the signal disturbance from n-well CG to the adjacent blocks through the substrate [11,12], as well as the slow erasing speed.…”

Low temperature below 200 °C solution processed tunable flash memory device without tunneling and blocking layer

“…From the sweep direc-tion of the CV curve it is inferred that gate injection of carriers controls the memory operation. Although conventional flash memory architecture follows channel injection of carriers [20], the interface degrades fast in such devices [34]. Thus, compared to channel injected devices, gate-injected devices show higher endurance which is one of the key requirements of memory operation [35].…”

“…Thus, compared to channel injected devices, gate-injected devices show higher endurance which is one of the key requirements of memory operation [35]. Because of such advantages, the quest for efficient gateinjected flash memory devices is ongoing [34][35][36][37]. A systematic change in the hysteresis window as a function of heating temperature is presented in Fig.…”