Full Scan Structure Application in the Design of 16 Bit MCU

Pan, Hong Bo; Song, Ming Xin; Xing, Jianchun

doi:10.4028/www.scientific.net/amr.981.78

Cited by 3 publications

(2 citation statements)

References 5 publications

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“…From these values, we are ensuring that all the transistors are in saturation. Or if they are not in saturation, widths of these transistors are changed accordingly to make them saturated (see Table 2) [29][30][31][32][33][34][35].…”

Section: Procedures (Milestone1)mentioning

confidence: 99%

An NMOS transistor-based high-gain operational amplifier designed in 0.25-micron CMOS technology

Abdul-jabbar,

Rashid,

RASHEED

et al. 2023

AJEST

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This project describes in detail the process of designing and simulating at first a one stage folded cascode operational amplifier using 0.25 um CMOS Technology with the self-biasing scheme for the NMOS differential input stage is discussed here. The design of the required circuits is done using the LTspice simulator. We will see that the simulation results approximately matches with the desired and theoretically calculated performance values. We are changing width values to bring all the transistors of the circuit in saturation. Then two Stage Folded Cascode Operational Amplifier with Miller compensation technique for the NMOS input. The operational amplifiers circuit is designed with 0.25 µm CMOS Technology using LTspice software. The applied methodology to implement the circuit design for a given specification has clearly described including all the design equation has been presented. All the parameter like DC Gain and Phase Margin (PM) are presented and discussed. Finally, we have got after performance analysis that designed circuit based on NMOS input provide a 96 DC Gain.

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Section: Procedures (Milestone1)mentioning

confidence: 99%

An NMOS transistor-based high-gain operational amplifier designed in 0.25-micron CMOS technology

Abdul-jabbar,

Rashid,

RASHEED

et al. 2023

AJEST

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“…Design for Testability (or DFT) is the acronym for this approach. Furthermore, it enhances a chip with the property of "testability" [8].…”

Section: Introductionmentioning

confidence: 99%

Design For Testability Method To Sequential Circuit

RASHEED,

Rashid,

Bin Hamzah

et al. 2023

AJEST

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As the complexity of logic devices increased, it required more time and effort to manually design and verify tests, it was difficult to estimate test coverage, and the tests ran too slowly. This method is known as functional testing. Therefore, the industry adopted a design for test (DFT) strategy in which the design was updated to make testing simpler. In this work, a full scan testability method is going to be implemented to a sequential circuit (CUT). The CUT consists of at 6 D flip-flops and 10 logic gates. This CUT was designed using quartus prime software. The following steps are going to be implemented in this work: First, simulate the fault free circuit. Second, three faults were injected and tested to check if they can be detected or not. Finally, analyze the obtained results in terms of (what is the test pattern needed, how the fault can be observed at output).

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Design of a High Precision Low Temperature Drift Oscillation Circuit Based on CMOS Technology

Pan

2020

2020 IEEE 3rd International Conference on Electronics Technology (ICET)

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Full Scan Structure Application in the Design of 16 Bit MCU

Cited by 3 publications

References 5 publications

An NMOS transistor-based high-gain operational amplifier designed in 0.25-micron CMOS technology

An NMOS transistor-based high-gain operational amplifier designed in 0.25-micron CMOS technology

Design For Testability Method To Sequential Circuit

Design of a High Precision Low Temperature Drift Oscillation Circuit Based on CMOS Technology

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