Design For Testability Method To Sequential Circuit

Abstract

As the complexity of logic devices increased, it required more time and effort to manually design and verify tests, it was difficult to estimate test coverage, and the tests ran too slowly. This method is known as functional testing. Therefore, the industry adopted a design for test (DFT) strategy in which the design was updated to make testing simpler. In this work, a full scan testability method is going to be implemented to a sequential circuit (CUT). The CUT consists of at 6 D flip-flops and 10 logic gates. This CUT was designed using quartus prime software. The following steps are going to be implemented in this work: First, simulate the fault free circuit. Second, three faults were injected and tested to check if they can be detected or not. Finally, analyze the obtained results in terms of (what is the test pattern needed, how the fault can be observed at output).