Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance Applications

Optimization of Structure and Electrical Characteristics for Four-Layer Vertically-Stacked Horizontal Gate-All-Around Si Nanosheets Devices

“…Furthermore, a larger I ON / I OFF ratio and smaller values of SS s and DIBL s for 25.8 nm- L g devices is achieved for the fabricated stacked GAA Si NS devices by the optimization of suppression of parasitic channels and device’s structure. The results indicated that the stacked GAA Si NS devices fabricated have much better comprehensive characteristics compared with those of the compared devices reported [ 10 , 11 , 12 , 13 , 30 ].…”

“…In order to achieve a compatible fabrication approach with the mainstream FinFET process and improve the driving ability of the GAA NW/NS devices, stacked GAA Si NW/NS FETs have been proposed using conventional gate-last process, which provides a simple integration method by releasing NW channels from multilayer epitaxial GeSi/Si stacks in replacement high-k dielectric/metal gate (HK/MG) trenches [ 11 ]. However, compared with the traditional bulk FinFET architecture, the fabrication of stacked GAA Si NW/NS FETs suffers from a lot of challenges, such as NSs channel release, steep fin etch, inter-diffusion restriction of GeSi/Si stacks, inner spacers, and so on [ 12 , 13 ]. In addition, conventional techniques of parasitic sub-fin channel suppression, such as halo implantation for planar device and punchthrough stop (PTS) doping for bulk FinFET, are not suitable for GAA Si NW/NS devices, which need new approaches to reduce the leakage of parasitic sub-fin channel and improve device’s subthreshold characteristics [ 14 ].…”

State of the Art and Future Perspectives in Advanced CMOS Technology

“…As CMOS technology enters the 3 nm node, GAA nanosheet/nanowire becomes the most powerful competitor to replace FinFET technology because of its excellent control of SCEs [ 189 , 190 ]. As it was mentioned above, GAA devices mainly have two forms, horizontal [ 191 , 192 ] and vertical [ 46 , 193 , 194 ], and selective etching plays a very important role in these manufacturing processes. For the preparation of horizontal nanowires shown in Figure 32 , there are three main steps that require precise selective etching to prepare inner spacers and release dummy gates and nanowire channels.…”

“…The thin thicknesses will increase the leakage and parasitic capacitance. The thicker thicknesses will increase the resistance between S/D when the device is turned on [ 191 , 192 ]. Inner spacers have greater challenges than conventional spacers where a higher etching selection ratio and etching accuracy are required [ 195 ].…”

Narrow Sub-Fin Technique for Suppressing Parasitic-Channel Effect in Stacked Nanosheet Transistors

“…Higher the GP doping concentration in the scaled GAA NS-FET may results in other issues, such as bandto-band tunneling (BTBT) induced serious gate-induced drain leakage (GIDL) effect [9], carrier velocity degradations and performance variations [10]. Other approaches for suppressing parasitic-channel effect, such as bottom dielectric isolation approach [11] with additional complexity or silicon on insulator (SOI) substrates [12], have also been reported for better PEC control.…”