Full-Bit Functional, High-Density 8 Mbit One Transistor–One Capacitor Ferroelectric Random Access Memory Embedded within a Low-Power 130 nm Logic Process

Abstract

We report the electrical properties of a full-bit functional 8 Mbit one transitor-one capacitor (1T-1C) embedded ferroelectric random access memory (eFRAM) fabricated within a low-leakage 130 nm 5 lm Cu interconnect complementary metal oxide semiconductor (CMOS) logic process. To increase manufacturability and reliability margins, we have introduced a single-bit substitution methodology that replaces bits at the low-end of the original distribution with redundant elements leading to an increased signal margin. Further, we have fabricated a digital signal processor (DSP) using the eFRAM process flow and have shown that the operating frequency is nearly the same relative to the CMOS baseline. With the development of logiccompatible eFRAM, we have created a technology platform that enables ultra-low-power devices.

Overview of candidate device technologies for storage-class memory

“…In summary, most of the recent work on FeRAM seems to address embedded memory applications [40,41] building on the strengths of FeRAM (CMOS compatibility, low-power, and low-voltage operation) and avoiding its weaknesses (difficulty in scaling to ultrasmall cell size). On the other hand, FeRAM is one of the most commercially successful new NVM alternatives, having been used in the Sony PlayStation ** 2 system [32].…”

Piezoresponse Force Microscopy Studies of Switching Behavior of Ferroelectric Capacitors on a 100-ns Time Scale

“…Small capacitors, where polarization reversal is dominated by domain wall motion, switch faster at high fields but more slowly at low fields while larger capacitors do the reverse. Among nonvolatile memory technologies, ferroelectric random access memory (FeRAM) is one of the most promising and technologically advanced [1]. Manufacturers of FeRAMs have recently lowered the film thickness below 100 nm, which introduces thickness scaling of both static properties and dynamic switching parameters of ferroelectric capacitors.…”

“…The capacitor size criterion for the switching to be limited by the domain wall speed rather than by nucleation has been formulated by Scott under the assumption of the field-independent v=R ratio [1,23]. The wall-speed limited switching time is determined by t w 2NRv 2 =9 ÿ1=3 , where N is a density of nucleation sites.…”

“…The nucleation time is given by t n 1= NRA , where A is the capacitor lateral area. Hence, for nucleation time to have a negligible effect on switching it is required that v= NR A 3=2 , and for PZT capacitors yields that the critical size A is 1 m 2 [1]. A difference between n and w makes this criterion a function of the applied field: Using the extrapolation values of v 1 and R 1 from the plot in Fig.…”

Oxygen Vacancy Kinetics Mechanism of the Negative Forming-Free Process and Multilevel Resistance Based on Hafnium Oxide RRAM

“…With the advent of the big data era, the explosive amount of information requires researchers to constantly seek for memory such as high-speed operation, large on/off ratio, reliable switching endurance, long high-temperature lifetime, multivalue storage, and high device yield [1]. Based on these requirements, researchers worked on developing new storage and have achieved good results such as phase change memory (PCM) [2][3][4], ferroelectric random access memory (FRAM) [5][6][7], and flash memory [8][9][10]. As a candidate for next-generation memory storage, resistive random access memory (RRAM) has attracted more and more researchers' attention because it has the potential to achieve the excellent storage properties mentioned above [11][12][13].…”