Front-end CMOS chipset for fiber-based gigabit Ethernet

Yoon, Ty; Jalali, Bahram

doi:10.1109/vlsic.1998.688079

Cited by 13 publications

(7 citation statements)

References 1 publication

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“…For (under-damped response) the bandwidth ( 3-dB frequency) can be given as (9) In this case, the amplitude of the normalized gain has a peak given by (10) (4) can be obtained if the loop gain is increased to 3.3, which also increases the peak to 1.2 (or 1.5 dB). dc gain is calculated by (11) As expected in feedback amplifiers, reduces as increases when is kept constant.…”

Section: Uniform Cmamentioning

confidence: 99%

“…High voltage gain from dc to several gigahertz frequencies is acquired by cascading several gain stages in the form of multistage amplifiers (MAs). Designing MAs with a bandwidth that is as large as the bit rate of the signal [1] (e.g., 10 GHz for SONET OC-192) using standard CMOS technology is still a challenging issue. Employing the bandwidth enhancement techniques such as capacitance neutralization [1], capacitive-peaking [2], bootstrapping [3], [4] and shunt-peaking [5]- [7] expands the bandwidth of gain stages, thus broadens the overall bandwidth [2]- [11].…”

Section: Introductionmentioning

confidence: 99%

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Uniform Design of Multi-Peak Bandwidth Enhancement Technique for Multistage Amplifiers

Samadi

Karsilayan

2007

IEEE Trans. Circuits Syst. I

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A new technique for designing uniform multistage amplifiers (MAs) for high-frequency applications is introduced. The proposed method uses the multi-peak bandwidth enhancement technique while it employs identical, simple and inductorless stages. The intrinsic capacitances within transistors are exploited by the active negative feedbacks to expand the bandwidth. While all stages of the proposed MA topology are identical, the gain-bandwidth product can be extended several times. Using the proposed topology, a six-stage amplifier in TSMC 0.35-m CMOS process was designed. Measurement results show that the gain can be varied between 16 and 44 dB within 0.7-3.2-GHz bandwidth with less than 5.2-nV Hz noise. Die area of the amplifier is 175 m 300 m.

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Section: Uniform Cmamentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Uniform Design of Multi-Peak Bandwidth Enhancement Technique for Multistage Amplifiers

Samadi

Karsilayan

2007

IEEE Trans. Circuits Syst. I

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“…This capacitance is typically ≈70-200 fF, which is significant for gigahertz circuitry considering that the maximum realizable inductance is only ≈4 nH. Thus, although bondwires have been used as shunt-peaking elements, the net improvement in bandwidth is only ≈10-15% [2]. Moreover, differential implementations of shunt-peaked amplifiers experience a degradation in power-supply rejection ratio (PSRR) because of the inductance mismatch between the two bondwires.…”

Section: On-chip Shunt-peakingmentioning

confidence: 99%

Bandwidth extension in CMOS with optimized on-chip inductors

Mohan

Hershenson²,

Boyd

et al. 2000

IEEE J. Solid-State Circuits

362

146

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We present a technique for enhancing the bandwidth of gigahertz broad-band circuitry by using optimized on-chip spiral inductors as shunt-peaking elements. The series resistance of the on-chip inductor is incorporated as part of the load resistance to permit a large inductance to be realized with minimum area and capacitance. Simple, accurate inductance expressions are used in a lumped circuit inductor model to allow the passive and active components in the circuit to be simultaneously optimized. A quick and efficient global optimization method, based on geometric programming, is discussed. The bandwidth extension technique is applied in the implementation of a 2.125-Gbaud preamplifier that employs a common-gate input stage followed by a cascoded common-source stage. On-chip shunt peaking is introduced at the dominant pole to improve the overall system performance, including a 40% increase in the transimpedance. This implementation achieves a 1.6-k transimpedance and a 0.6-A input-referred current noise, while operating with a photodiode capacitance of 0.6 pF. A fully differential topology ensures good substrate and supply noise immunity. The amplifier, implemented in a triple-metal, single-poly, 14-GHz , 0.5-m CMOS process, dissipates 225 mW, of which 110 mW is consumed by the 50-output driver stage. The optimized on-chip inductors consume only 15% of the total area of 0.6 mm 2 .

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“…Several researchers have realized 1.25 Gbps pre-amplifier with narrow dynamic range in 0.6 ptm CMOS process [1][2]. So it is possible to realize 622 Mbps pre-amplifier with low noise and wide dynamic range in 0.6 ptm CMOS process.…”

Section: Introductionmentioning

confidence: 99%

A Low Noise, Wide Dynamic Range Pre-amplifier with Automatic Gain Control for SDH/SONET (STM4/OC12) in 0.6 μm CMOS Process

Peng

Wang

2007

2007 International Conference on Microwave and Millimeter Wave Technology

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A low noise, wide dynamic range pre-amplifier for SDH/SONET (STM4/OC12) in 0.6 pm standard CMOS process is presented. Low noise is achieved by using transimpedance amplifier of multi-stage amplification and low drop-out regulator. Wide dynamic range is achieved by using automatic gain control and input DC cancellation. The amplifier exhibits differential transimpedance gain of 103.4 dBQ (147.91 kQ), -3 dB bandwidth of 446 MHz, and equivalent input noise current density of 2.57 pA/fHz . The optical overload, the power supply rejection ratio and the power consumption are +3 dBm, larger than 44 dB from DC to 30 MHz, 287 mW, respectively.

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Front-end CMOS chipset for fiber-based gigabit Ethernet

Cited by 13 publications

References 1 publication

Uniform Design of Multi-Peak Bandwidth Enhancement Technique for Multistage Amplifiers

Uniform Design of Multi-Peak Bandwidth Enhancement Technique for Multistage Amplifiers

Bandwidth extension in CMOS with optimized on-chip inductors

A Low Noise, Wide Dynamic Range Pre-amplifier with Automatic Gain Control for SDH/SONET (STM4/OC12) in 0.6 μm CMOS Process

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Front-end CMOS chipset for fiber-based gigabit Ethernet

Cited by 13 publications

References 1 publication

Uniform Design of Multi-Peak Bandwidth Enhancement Technique for Multistage Amplifiers

Uniform Design of Multi-Peak Bandwidth Enhancement Technique for Multistage Amplifiers

Bandwidth extension in CMOS with optimized on-chip inductors

A Low Noise, Wide Dynamic Range Pre-amplifier with Automatic Gain Control for SDH/SONET (STM4/OC12) in 0.6 &#x003BC;m CMOS Process

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Product

Resources

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A Low Noise, Wide Dynamic Range Pre-amplifier with Automatic Gain Control for SDH/SONET (STM4/OC12) in 0.6 μm CMOS Process