Bandwidth extension in CMOS with optimized on-chip inductors

Abstract

We present a technique for enhancing the bandwidth of gigahertz broad-band circuitry by using optimized on-chip spiral inductors as shunt-peaking elements. The series resistance of the on-chip inductor is incorporated as part of the load resistance to permit a large inductance to be realized with minimum area and capacitance. Simple, accurate inductance expressions are used in a lumped circuit inductor model to allow the passive and active components in the circuit to be simultaneously optimized. A quick and efficient global optimization method, based on geometric programming, is discussed. The bandwidth extension technique is applied in the implementation of a 2.125-Gbaud preamplifier that employs a common-gate input stage followed by a cascoded common-source stage. On-chip shunt peaking is introduced at the dominant pole to improve the overall system performance, including a 40% increase in the transimpedance. This implementation achieves a 1.6-k transimpedance and a 0.6-A input-referred current noise, while operating with a photodiode capacitance of 0.6 pF. A fully differential topology ensures good substrate and supply noise immunity. The amplifier, implemented in a triple-metal, single-poly, 14-GHz , 0.5-m CMOS process, dissipates 225 mW, of which 110 mW is consumed by the 50-output driver stage. The optimized on-chip inductors consume only 15% of the total area of 0.6 mm 2 .

Shunt peaking in neural membranes

“…In addition, the FDR reduces signal distortion by the photoreceptor membrane (electronic supplementary materials), which is important for a wide-pass filter [6]. Shunt peaking achieves this without incurring the deleterious effects of reducing the microvillar membrane area [13,14], or compromising stability and minimum-phase (electronic supplementary materials).…”

“…The usual means of improving bandwidth without sacrificing gain is miniaturization [5] but there are others. One is shunt peaking; the improvement of the GBWP through the addition of inductive elements [6].…”

Tractable approximate robust geometric programming

“…Geometric programming has been used in various fields since the late 1960s; early applications of geometric programming can be found in the books Avriel (1980), Duffin et al (1967), Zener (1971) and the survey papers Ecker (1980), Peterson (1976), Boyd et al (2007). More recent applications can be found in various fields including circuit design Chen et al 2000;Dawson et al 2001;Daems et al 2003;Hershenson 2002;Hershenson et al 2001;Mohan et al 2000;Sapatnekar 1996;Singh et al 2005;Sapatnekar et al 1993;Young et al 2001), chemical process control (Wall et al 1986), environment quality control (Greenberg 1995), resource allocation in communication systems (Dutta and Rama 1992), information theory (Chiang and Boyd 2004;Karlof and Chang 1997), power control of wireless communication networks (Kandukuri and Boyd 2002;O'Neill et al 2006), queue proportional scheduling in fading broadcast channels (Seong et al 2006), and statistics (Mazumdar and Jefferson 1983).…”

Digital Circuit Optimization via Geometric Programming

“…Other problems in digital circuit design where GP plays a role include buffering and wire sizing Wong 1999, 2001a), sizing and placement (Chen et al 2000), yield maximization , Patil et al 2005, parasitic reduction (Qin and Cheng 2003), clock tree design (Vittal and Marek-Sadowska 1997), and routing (Borah et al 1997). Geometric programming has also been used for the design of nondigital circuits, e.g., analog circuits (Dawson et al 2001, Hershenson 2003, Hershenson et al 1998, Mandal and Visvanathan 2001, Vanderhaegen and Brodersen 2004, mixed-signal circuits (Colleran et al 2003, Hassibi and Hershenson 2002, Hershenson 2002, and RF (radio frequency) circuits Mohan et al 1999Mohan et al , 2000Xu et al 2004). Geometric programming has also been used in floorplanning, for both analog and digital circuits (Moh et al 1996).…”