From the ESD robustness of products to the system ESD robustness

Stadler, Wolfgang; Bargstädt-Franke, S.; Brodbeck, T.; Gaertner, Reinhold; Goroll, Michael; Gosner, H.; Jensen, Charlotte Louise

doi:10.1109/eosesd.2004.5272634

Cited by 16 publications

(4 citation statements)

References 2 publications

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“…When the PC triggers on, the current is split in two: the PC sinks one part, its value being defined by the potential across the capacitor, the other part still charging the capacitor. When the TLP signal ends, the discharge is first accelerated by the conduction of the power clamp and then when the PC turns off it follows (6). Finally, the internal power supply voltage comes back to Vcrit 600 ns sooner with the PC than without the PC.…”

Section: B Analysismentioning

confidence: 99%

Investigation of Modeling System ESD Failure and Probability Using IBIS ESD Models

Monnereau

Caignet

Nolhier

et al. 2012

IEEE Trans. Device Mater. Relib.

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Due to growing number of embedded electronics, estimating failure related to system-level electrostatic discharge (ESD) consideration has become a major concern. In this paper, a behavioral modeling methodology to predict ESD failures at system level is proposed and validated. The proposed models enable time-domain simulation to determine the voltage and current waveforms inside and outside an integrated circuit during ESD events and then to predict the susceptibility of an electronic system to ESD. The purpose of this methodology is based on the improvement of Input/output Buffer Information Specification files widely used in signal integrity simulation. A simple case study is proposed to investigate the susceptibility of latch devices to transient stresses. Simulations and measurements are compared. Analytical formulations to determine the probability of susceptibility failure are proposed and compared with measurements.

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Section: B Analysismentioning

confidence: 99%

Investigation of Modeling System ESD Failure and Probability Using IBIS ESD Models

Monnereau

Caignet

Nolhier

et al. 2012

IEEE Trans. Device Mater. Relib.

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“…The measurement setup for the EFT test combined with the capacitive coupling clamp is shown in Fig. 16…”

Section: Eft Testmentioning

confidence: 99%

New Transient Detection Circuit for On-Chip Protection Design Against System-Level Electrical-Transient Disturbance

Ker

Yen

2010

IEEE Trans. Ind. Electron.

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A new transient detection circuit for on-chip protection design against system-level electrical-transient disturbance is proposed in this paper. The circuit function to detect positive or negative electrical transients under system-level electrostatic-discharge (ESD) and electrical-fast-transient (EFT) testing conditions has been investigated by HSPICE simulation and verified in silicon chip. The experimental results in a 0.18-µm complementary-metal-oxide-semiconductor (CMOS) process have confirmed that the new proposed on-chip transient detection circuit can successfully memorize the occurrence of system-level electrical-transient disturbance events. The output of the proposed on-chip transient detection circuit can be used as a firmware index to execute the system recovery procedure. With hardware/firmware codesign, the transient disturbance immunity of microelectronic products equipped with CMOS integrated circuits under system-level ESD or EFT tests can be significantly improved.

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“…Over the last few years, system-level electrostatic discharge (ESD) tests according to IEC 61000-4-2 (often referred as "IEC" or "GUN") [1] have been applied directly on standalone ICs or together with external ESD protection elements on board with a short discharge connection between ESD generator tip and devices under test (DUT) [2]. The motivations to test ICs according the IEC standard are manifold.…”

Section: Introductionmentioning

confidence: 99%

A TLP-based Human Metal Model ESD-generator for device qualification according to IEC 61000-4-2

Cao

Johnsson

Arndt

et al. 2010

2010 Asia-Pacific International Symposium on Electromagnetic Compatibility

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In the last years system-level electrostatic discharges tests according to IEC 61000-4-2 have become widely used for component ESD qualification although it suffers from poor reproducibility. To minimize the disadvantages a so called Human Metal Model (HMM) measurement technique is momentarily in discussion and the standardization committee (SP5.6, ESDA) is working on its definition. The current stress waveform of HMM is identical to the IEC 61000-4-2 one. In this paper a new HMM pulse generator set-up based on a TLP pulse generator will be discussed. To get a deeper insight in the HMM method, discrete components, on-chip ESD test structures as well as a LIN transceiver were evaluated with this technique. The gained measurement results are compared with those resulting out of the IEC tests.

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From the ESD robustness of products to the system ESD robustness

Cited by 16 publications

References 2 publications

Investigation of Modeling System ESD Failure and Probability Using IBIS ESD Models

Investigation of Modeling System ESD Failure and Probability Using IBIS ESD Models

New Transient Detection Circuit for On-Chip Protection Design Against System-Level Electrical-Transient Disturbance

A TLP-based Human Metal Model ESD-generator for device qualification according to IEC 61000-4-2

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