From 2D-planar to 3D-non-planar device architecture: A scalable path forward?

Abstract

The microelectronics industry is in the process of transitioning from 2D-planar devices to 3D-non-planar (FinFET). In this paper, a metric is developed to assess the impact of scaling and device performance on chip (circuit) power as it is migrated node-to-node. The impact of node migration is assessed at product level as it is moved from 32 nm (2D-planar) to 22 nm (3D-non-planar device). Some of the limitations of the existing 22 nm 3D-device is reviewed that may explain some of the short comings in the product performance. Going forward it is critical that in two areas the FinFET needs to be improved: Multi-V T implementation and move away from the tapered fin shape.

Evolution and performance analysis of quantum well FinFET for 3 nm technology node with type-II strained tri-layered hetero-channel system

“…Transistors are needed to be scaled down to relatively small size in sub-nanometer range instituting acceptable performances. However, there are various challenges faced by scaling mechanisms such as high access resistance relating to extreme thin body [1], or membrane-like structures, quantum effects involving multiple fins with different materials, manufacturability relating to the non-planar or 3D process integration and very constricted process control [2]. So, the inevitable progress gradually slowed down upon entering into the nano regime due to the rise of Short Channel Effects (SCEs) [3].…”