Design and Performance Analysis of 3-Fin 08 nm Physical Gate Length SOI FinFETs Employing Gate Stacked High-K Dielectrics

Nanda, Swagat; Kumari, Sapna; Dhar, Rudra Sankar

doi:10.1109/aespc59761.2023.10390364

2023 IEEE 3rd International Conference on Applied Electromagnetics, Signal Processing, &Amp; Communication (AESPC) 2023

DOI: 10.1109/aespc59761.2023.10390364

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Design and Performance Analysis of 3-Fin 08 nm Physical Gate Length SOI FinFETs Employing Gate Stacked High-K Dielectrics

Swagat Nanda,

Sapna Kumari,

Rudra Sankar Dhar

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Design and Performance Analysis of 3-Fin 08 nm Physical Gate Length SOI FinFETs Employing Gate Stacked High-K Dielectrics

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