Frequency-range enhanced delay locked loop based on varactor-loaded and current-controlled delay elements

Kazeminia, Sarang

doi:10.1016/j.aeue.2020.153477

Cited by 6 publications

(2 citation statements)

References 28 publications

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“…Note that adding dummy loads to other cells can considerably improve the quality of averaging in Ref. [18]. As a result, 0.25 unit interval (UI) of timing margin is reserved on the setup time (VCDL_ck4) and 0.3125 UI of timing margin is secured on the hold time (VCDL_ck11), respectively.…”

Section: Architecture and Circuit Implementation Of The Output Drivermentioning

confidence: 99%

A CMOS slew‐rate controlled output driver with low process, voltage and temperature variations using a dual‐path signal‐superposition technique

Gui

Tang

et al. 2022

IET Circuits, Devices & Syst

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A dual‐path open‐loop slew‐rate (SR) controlled Complementary Metal Oxide Semiconductor (CMOS) driver is presented in this study. The proposed output driver incorporates a delay‐locked loop (DLL) to minimise the SR variations over process, voltage and temperature, generating delayed versions of transmitted signal by sampling the input data with adjacent phases of the clock from the DLL. A dual‐path open‐loop signal‐superposition technique is introduced to suppress the high‐frequency components of the output driver and thus improves the SR of the CMOS driver. The proposed CMOS output driver achieves a maximum SR of 1.00 and <0.35 V/ns variation operating at 500 Mbps over 32 corners. Both the conventional CMOS driver and the proposed SR controlled output driver were fabricated in a 0.18 μm CMOS process. The proposed driver occupies a compact area of 0.088 mm2 and consumes 55.27 mW with a 1.8 V supply voltage. Measurement results show that the SR of the proposed output driver is <0.816 V/ns, corresponding to 62% reduction compared with that of a conventional output driver, and the total jitter is <0.16 unit interval.

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Section: Architecture and Circuit Implementation Of The Output Drivermentioning

confidence: 99%

A CMOS slew‐rate controlled output driver with low process, voltage and temperature variations using a dual‐path signal‐superposition technique

Gui

Tang

et al. 2022

IET Circuits, Devices & Syst

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show abstract

“…The requirement of an additional bias voltage is another drawback. [10] utilizes diode-connected devices to eliminate dead zone but also causes the charge pump to turn off slowly. The structure of conventional reset-path based PD.…”

Section: Introductionmentioning

confidence: 99%

Dead-Zone Free, Static Phase Offset Improvement Phase Detector for High Resolution and Low Jitter Delay-Locked Loop

Wu,

Huang,

Sun

et al. 2023

J. Phys.: Conf. Ser.

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This work presents a phase detector (PD) having dead-zone free and static phase offset improvement performance. The proposed phase detector inherits the low power consumption advantage of the conventional phase detector using two true-single-phase clocking (TSPC) DFFs. It also effectively reduces the static phase offset, even in the presence of inevitable charge pump current mismatch. And the dead-zone problem of conventional TSPC PD is overcome by using a falling edge delay inverter. The PD is implemented using a standard 180nm CMOS technology. The dimension of the PD’s layout is 11μm×16μm. Post-layout simulation shows that the power consumption is 53.8μW at 250MHz and 160μW at 800MHz. It achieves tiny static phase offset even if the charge pump has a 3.8% current mismatch.

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A low power and jitter delay cell with pulse width modulation for wide range delay lock loops

Modanlou

Ardeshir

Gholami

2021

Microelectronics Journal

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Frequency-range enhanced delay locked loop based on varactor-loaded and current-controlled delay elements

Cited by 6 publications

References 28 publications

A CMOS slew‐rate controlled output driver with low process, voltage and temperature variations using a dual‐path signal‐superposition technique

A CMOS slew‐rate controlled output driver with low process, voltage and temperature variations using a dual‐path signal‐superposition technique

Dead-Zone Free, Static Phase Offset Improvement Phase Detector for High Resolution and Low Jitter Delay-Locked Loop

A low power and jitter delay cell with pulse width modulation for wide range delay lock loops

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