Frequency-Independent Parametric Built in Test Solution for PLLs with Low Speed Test Resources

Abstract

Phase Locked Loops (PLLs) are required to meet analog specifications such as lock time, phase error, jitter in addition to the frequency lock test in production. Parametric testing of PLLs is resource intensive and requires high precision hardware on the Automatic Test Equipment (ATE). This paper proposes a Built in Self Test (BIST) scheme to perform functional and parametric testing using low frequency ATE resources. The BIST module is independent of the PLL frequency and can be used effectively in multi-PLL System-on-a-Chip (SoC) modules. The scheme uses the Phase Detector (PD) output signature to test for lock and transient response using a digital BIST module. The BIST scheme is designed without impacting the mission mode performance by not perturbing analog nodes and the phase sensitive feedback loop. The test methodology enables parametric testing for process variation and specification compliance while using minimal external test resources. Process and operating condition independence is a critical factor to ensure compatibility with volume manufacturing and test environments.

All‐digital built‐in self‐test scheme for charge‐pump phase‐locked loops

“…It avoids the effects of additional MUXs on the performance of circuit under test (CUT) and the measurement accuracy, but its resolution is limited by the target CUT rather than the capability of the BIST circuit. In [16], a BIST scheme to perform testing of both catastrophic and parameter faults in a PLL using low frequency ATE resources is suggested. The scheme is robust and is independent of the fabrication process corner and the operating conditions, but the fault coverage is relatively low.…”

“…Many different structures of time‐to‐digital converter have been used in the method, such as that based on the delay line, the Vernier ring oscillator, and the time‐to‐voltage converter. Though it achieves a very excellent time resolution, the additional test circuits are usually too complex with high area overhead. Defect‐oriented test (DOT) [15–22]. …”

Built‐in self‐test structure for fault detection of charge‐pump phase‐locked loop

“…However, the test circuit is complex and it is still time consuming. (iii) Defect-oriented test (DOT) [12][13][14][15][16][17][18][19][20][21][22], which targets the presence of physical defects in a PLL. Based on the principle of physical defects will affect the performance of PLL, this technique could almost detect any fault in PLL.…”

“…Since it made some modification on analogue node, the influence on the performance of PLL cannot be ignored. In [15], Sachin Dileep Dasnurkar proposed that a BIST scheme enables testing of both catastrophic and marginal failures in the PLL, but the fault coverage of catastrophic failures is relatively low. In [16], a BIST method by measuring the oscillation frequency response voltage-controlled oscillator (VCO) showed very excellent fault coverage (100%), but it only focused on testing the VCO.…”