Frequency dispersion in III-V metal-oxide-semiconductor capacitors

Abstract

A recombination-controlled tunneling model is used to explain the strong frequency dispersion seen in the accumulation capacitance and conductance of dielectric/n-In0.53Ga0.47As metal-oxide-semiconductor capacitors. In this model, the parallel conductance is large when, at positive gate biases, the metal Fermi level lines up with a large density of interface states in the In0.53Ga0.47As band gap. It is shown that the model explains in a semi-quantitative manner the experimentally observed capacitor characteristics, including a peak in parallel conductance/frequency (Gp/ω) versus log frequency curves at positive gate bias and the dependence of the frequency dispersion on the dielectric thickness.

Plasma Enhanced Atomic Layer Deposition Passivated HfO₂/AlN/In_0.53Ga_0.47As MOSCAPs With Sub-Nanometer Equivalent Oxide Thickness and Low Interface Trap Density

“…From the C-V responses, inversion layer still exists at negative-bias region, implying a very good interface quality [2], [3], [10]. As the gate oxides shrinking down, the accumulation frequency dispersion is seriously large for some unclear reasons [21]. One possible explanation may be the plasma induced damage caused by ion bombardment that correlated to the degradation of metal/high-k interface.…”

Influence of plasma-based in-situ surface cleaning procedures on HfO2/In0.53Ga0.47As gate stack properties

“…The large frequency dispersion in accumulation is typical for highly scaled MOSCAPs, for reasons that currently not fully understood. [15][16][17] The measured accumulation capacitances at low frequencies suffer from leakage artifacts; however, leakage is not expected to be an issue for transistors with gate dimensions much smaller than the MOSCAPs investigated here. In particular, the current density was measured to be less than 2 mA/cm 2 at 2 V. At frequencies not affected by leakage, the measured accumulation capacitance dispersion is slightly smaller in the sample cleaned using recipe B than that cleaned using recipe A, indicating a reduced (interface) trap density.…”

Accumulation capacitance frequency dispersion of III-V metal-insulator-semiconductor devices due to disorder induced gap states

“…1,2,[4][5][6][7]15,16,[24][25][26] All of these models require transport of carriers from the crystalline semiconductor into either a disordered and defective interfacial region or into defects within the bulk of the dielectric itself. All of these models begin with the results of Heiman and Warfield 27 whereby the impedance associated with a trap a distance, x, away from the outermost layer of the undisrupted crystalline semiconductor can be calculated by assuming that it has a trapping time constant given by…”