Accumulation capacitance frequency dispersion of III-V metal-insulator-semiconductor devices due to disorder induced gap states

Abstract

Articles you may be interested inGate-control efficiency and interface state density evaluated from capacitance-frequency-temperature mapping for GaN-based metal-insulator-semiconductor devices Effects of interface states and temperature on the C -V behavior of metal/insulator/AlGaN/GaN heterostructure capacitors Interface states in polymer metal-insulator-semiconductor devices J. Appl. Phys. 98, 073710 (2005); 10.1063/1.2081109Characteristics of an indium antimonide metal-insulator-semiconductor structure prepared by remote plasma enhanced chemical vapor depositionThe origin of the anomalous frequency dispersion in accumulation capacitance of metal-insulatorsemiconductor devices on InGaAs and InP substrates is investigated using modeling, electrical characterization, and chemical characterization. A comparison of the border trap model and the disorder induced gap state model for frequency dispersion is performed. The fitting of both models to experimental data indicate that the defects responsible for the measured dispersion are within approximately 0.8 nm of the surface of the crystalline semiconductor. The correlation between the spectroscopically detected bonding states at the dielectric/III-V interface, the interfacial defect density determined using capacitance-voltage, and modeled capacitance-voltage response strongly suggests that these defects are associated with the disruption of the III-V atomic bonding and not border traps associated with bonding defects within the high-k dielectric. V C 2014 AIP Publishing LLC.

Highly-stable and low-state-density Al2O3/GaN interfaces using epitaxial n-GaN layers grown on free-standing GaN substrates

“…The border trap model is common for traditional III-V MOS system using GaAs, InP, and InGaAs. [35][36][37][38] In those cases, remarkable frequency dispersion at accumulation bias in the experimental C-V curves is the most characteristic feature for the border trap model. [35][36][37][38] Border traps have long time constants as they interact with the conduction band electrons via tunneling, leading to large frequency dispersion even at accumulation bias.…”

Electrical properties of GaAs metal–oxide–semiconductor structure comprising Al2O3 gate oxide and AlN passivation layer fabricated in situ using a metal–organic vapor deposition/atomic layer deposition hybrid system

“…Under this consideration, interface states are located slightly far away from the dielectric/GaAs interface and can be modeled either as border traps in dielectrics near the MOS interface 51,52 or as disorder-induced gap states (DIGS) in semiconductors. 5,53 As shown in Figure 6, the incorporated nitrogen was distributed in the Al 2 O 3 layer with spatial width (identified as AlO x N y region) near the MOS interface. Its presence is believed to contribute to the reduction in accumulation dispersion.…”

“…52 In another study, Galatage et al identified defects in the semiconductor located within 0.8 nm from the surface as the origin of accumulation dispersion in In 0.53 Ga 0.47 As MOS capacitors. 53 In the present experiment, however, we should focuse on the semiconductor because only the nature of the semiconductor was altered. Thus, crystal orientation can impact on the trap states in GaAs located near the surface.…”

“…The plateau loss was attributed to the presence of interface states located slightly far away from the dielectric/GaAs interface in the dielectrics (border traps) or semiconductor (DIGS). 52,53 Brammertz et al simulated the admittance response of n-type InP MOS capacitors featuring border traps, which showed a large plateau in the G-V -f map and accumulation dispersion in the C-V curve. 52 In another study, Galatage et al identified defects in the semiconductor located within 0.8 nm from the surface as the origin of accumulation dispersion in In 0.53 Ga 0.47 As MOS capacitors.…”

Multi-frequency inversion-charge pumping for charge separation and mobility analysis in high-k/InGaAs metal-oxide-semiconductor field-effect transistors

“…A distance (x) for the spatial location of the border traps relative to the In 0.53 Ga 0.47 As interface can be estimated using the relationship 33 x ¼ k lnðt=sÞ; (7) where k is the attenuation coefficient and t is the tunnelling time. Assuming a k value within the typical range of 9.8 Â 10 À9 -1.25 Â 10 À8 cm reported for the Al 2 O 3 / In 0.53 Ga 0.47 As interface [16][17][18]21,30 and considering that N CP saturation is reached at t $ 5 ls (Fig. 6), we obtain a distance x of about 1.6-2.1 Å from the interface.…”