FPGA routing and routability estimation via Boolean satisfiability

Wood, R. Glenn; Rutenbar, Rob A.

doi:10.1145/258305.258322

Cited by 42 publications

(20 citation statements)

References 29 publications

(24 reference statements)

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“…Boolean satisfiability (SAT) solvers and their extensions, such as quantified Boolean formula satisfiability (QBF) solvers and pseudo-Boolean satisfiability (PBS) solvers, have become attractive tools for solving theoretically intractable problems in VLSI CAD, in areas such as testing [21], verification [25] and physical design [27]. Furthermore, any improvement to the state-of-theart in satisfiability solving translates into an immediate benefit to all satisfiability-based solutions.…”

Section: Introductionmentioning

confidence: 99%

Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability

Mangassarian

Veneris

Najm

2012

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-With lower supply voltages, increased integration densities and higher operating frequencies, power grid verification has become a crucial step in the VLSI design cycle. The accurate estimation of maximum instantaneous power dissipation aims at finding the worst-case scenario where excessive simultaneous switching could impose extreme current demands on the power grid. This problem is highly input-pattern dependent and is proven to be NP-hard. In this work, we capitalize on the compelling advancements in satisfiability solvers to propose a pseudo-Boolean satisfiability-based framework that reports the input patterns maximizing circuit activity, and consequently peak dynamic power, in combinational and sequential circuits. The proposed framework is enhanced to handle unit gate delays and output glitches. In order to disallow unrealistic input transitions, we show how to integrate input constraints in the formulation. Finally, a number of optimization techniques, such as the use of gate switching equivalence classes, are described to improve the scalability of the proposed method. An extensive suite of experiments on ISCAS85 and ISCAS89 circuits confirms the robustness of the approach compared to simulation-based techniques and encourages further research for low-power solutions using Boolean satisfiability.

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Section: Introductionmentioning

confidence: 99%

Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability

Mangassarian

Veneris

Najm

2012

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…For island-style (symmetric) FPGAs, some routing approaches via satisfiability has been done [Wood and Rutenbar 1998;Nam et al 1999Nam et al , 2001. They assumed that each wire segment spans only one block, used a heuristic global router to find a routing path (cells) for each net, and then used satisfiability to perform detailed routing in the cells along the globally routed paths.…”

Section: Introductionmentioning

confidence: 99%

Segmented channel routability via satisfiability

Hung

Song

Aboulhamid

et al. 2004

ACM Trans. Des. Autom. Electron. Syst.

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Segmented channel routing is fundamental to the routing of row-based FPGAs. In this paper, we study segmented channel routability via satisfiability. Our method encodes the horizontal and vertical constraints of the routing problem as Boolean conditions. The routability constraint is satisfiable if and only if the net connections in the segmented channel are routable. Empirical results show that the method is time-efficient and applicable to large problem instances.

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“…Fast -Both the methods are extremely fast. In contrast, methods like BDD based estimation [16] are very slow and sometimes exceeds incremental routing in runtimes. Usable -These methods estimate actual track usages and thus can used to get both global and local routing usages.…”

Section: Related Workmentioning

confidence: 99%