Segmented channel routability via satisfiability

Abstract

Segmented channel routing is fundamental to the routing of row-based FPGAs. In this paper, we study segmented channel routability via satisfiability. Our method encodes the horizontal and vertical constraints of the routing problem as Boolean conditions. The routability constraint is satisfiable if and only if the net connections in the segmented channel are routable. Empirical results show that the method is time-efficient and applicable to large problem instances.

Defect-Tolerant CMOL Cell Assignment via Satisfiability

“…Notice that if there are more than one solutions to the problem, the SAT solver tend to finish very fast. Satisfiability has been used to solve a variety of problems [7,13]. Many commercial CAD tools in industry also use SAT solvers in their CAD flow.…”

SAT based solutions for detailed routing of island style FPGA architectures

“…In [16] authors have proposed a route-based FPGA detailed routing approach using Boolean SAT and analyze the performance improvement over a previously proposed track-based approach [18]. An extension of the classical 2-layer routing in [6] for segmented channel routing using SAT for row based FPGAs was proposed in [9]. In [19], the authors propose a SAT-based methodology for detailed routing using the graph colouring approach for 2-pin net routes where graph colouring is represented as a Constraint Satisfaction Problem (CSP) and the variables are represented using if-then-else structures.…”

A genetic algorithm for segmented channel routing

“…Yang (2000) presented an algorithm using the weighted bipartite-matching approach to solve the k-SR problem. An algorithm solving k-SR based on SAT proposed by Hung, Song, Aboulhamid, Kennings, and Coppola (2004) and Nobuo (1999) used a gradual neural network to solve the k-SR problem. All the previous approaches only can solve the k-SR problem and they cannot deal with the USR problem directly.…”