On routing demand and congestion estimation for FPGAs

Balachandran, S.; Kannan, P.; Bhatia, D.

doi:10.1109/aspdac.2002.995008

Cited by 4 publications

(4 citation statements)

References 16 publications

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“…Further, we also ensure that the demand assigned is at least as much as the demand posed by any of the two-terminal pairs. This simple enhancement improves the quality of the estimation by as much as 103% compared to the FPGA model proposed in [2]. This is clearly illustrated in the Table 1, where the peak demands estimated by both the methods are compared against the actual peak demands obtained by performing detailed routing using VPR.…”

Section: Enhancements To Lou's Modelmentioning

confidence: 90%

“…Thus demands are obtained on a channel by channel basis. Experiments on 20 large FPGA benchmarks are reported in [2].…”

Section: Lou's Methodsmentioning

confidence: 99%

“…In [2], we adapted the Lou's model to FPGA design flows. A rectangular grid was overlaid on an island-style FPGA, where a single grid element corresponds to a switchbox and its four incident half-channels.…”

Section: Lou's Methodsmentioning

confidence: 99%

“…They do not provide any solution to alleviate the problem. In [2], we established that the problem with segment overlaps applies to any two-terminal decomposition, including the RST based decomposition. Further, we claimed that even if a clever net decomposition may remove large net overlaps, the bounding boxes of the pairs may still overlap thus resulting in inaccuracies.…”

Section: Enhancements To Lou's Modelmentioning

confidence: 99%

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On metrics for comparing routability estimation methods for FPGAs

Kannan

Balachandran

Bhatia

2002

Proceedings of the 39th Conference on Design Automation - DAC '02

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Interconnect management is a critical design issue for large FPGA based designs. One of the most important issues for planning interconnection is the ability to accurately and efficiently predict the routability of a given design on a given FPGA architecture. The recently proposed routability estimation procedure, fGREP [6], produced estimates within 3 to 4% of an actual detailed router. Other known routability estimation methods include RISA [5], Lou's [7] method and Rent's rule based methods [1] [11] [9]. Comparing these methods has been difficult because of the different reporting methods used by the authors. We propose a uniform reporting metric based on comparing the estimates produced with the results of an actual detailed router on both local and global levels. We compare all the above methods using our reporting metric on a large number of benchmark circuits and show that the enhanced fGREP method produces tight estimates that outperform most other techniques.

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Section: Enhancements To Lou's Modelmentioning

confidence: 90%

“…Thus demands are obtained on a channel by channel basis. Experiments on 20 large FPGA benchmarks are reported in [2].…”

Section: Lou's Methodsmentioning

confidence: 99%

Section: Lou's Methodsmentioning

confidence: 99%

Section: Enhancements To Lou's Modelmentioning

confidence: 99%

See 2 more Smart Citations