FPGA realization and performance evaluation of fixed-width modified Baugh-Wooley multiplier

Abstract

Fixed-width multipliers are widely used in digital signal processing (DSP) applications such as finite impulse response filter (FIR), fast Fourier transform (FFT) and discrete cosine transform (DCT). Baugh-Wooley multiplier is a preferred choice for the realization of 2's complement multiplication operation used in these applications. This paper presents the hardware realization and performance evaluation of 8×8 fixedwidth modified Baugh-Wooley multiplier using state-of-the-art 7 series field programmable gate arrays (FPGAs) such as Virtex-7, Artix-7 and Zynq-7000, available from Xilinx. Different optimization goals are applied to the multiplier design and the performance is evaluated for area, speed and power. Simulation is done to verify the functionality of the design.

An area-optimized N-bit multiplication technique using N/2-bit multiplication algorithm

“…Where A H and B H are the most significant half bits of each number, A L and B L are the least significant half, while k = 2 n∕2 [18]. If the value of k is 2 1 , then it represents singlebit left shift. Therefore, if we have 16-bit number, then 2 8 would represent a left shift of eight bits.…”

“…The commonly used architectures include Baugh-Wooley and Booth multiplier. For multiplication of signed numbers, typically the Baugh-Wooley multiplier is preferred [1]. Radix-2 and Radix-4 booth multipliers were implemented in [2] for 8-bit and 16-bit multiplication.…”