FPGA Implementation of FEC Encoder with BCH &amp; LDPC Codes for DVB S2 System

Digdarsini, Durga; Mishra, Deepak; Mehta, Sanjay D.; Ram, T. V. S.

doi:10.1109/spin.2019.8711664

Cited by 11 publications

(9 citation statements)

References 1 publication

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“…In the field of satellite communications, many of the specific SDR implementations are focused on channel coding aspects [280]- [282]. Low-Density Parity-Check (LDPC) codes, which are the core of the FEC functionalities in the DBV-S2 and DVB-S2X standards, gained much of the interest in the community because their outstanding BER performance; close to Shannon limit at relatively low complexity and latency.…”

Section: A Phy and Mac: Software Defined Radio (Sdr) Basedmentioning

confidence: 99%

Satellite Communications in the New Space Era: A Survey and Future Challenges

Kodheli

Lagunas

Maturo

et al. 2021

IEEE Commun. Surv. Tutorials

600

428

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Satellite communications (SatComs) have recently entered a period of renewed interest motivated by technological advances and nurtured through private investment and ventures. The present survey aims at capturing the state of the art in SatComs, while highlighting the most promising open research topics. Firstly, the main innovation drivers are motivated, such as new constellation types, on-board processing capabilities, nonterrestrial networks and space-based data collection/processing. Secondly, the most promising applications are described i.e. 5G integration, space communications, Earth observation, aeronautical and maritime tracking and communication. Subsequently, an in-depth literature review is provided across five axes: i) system aspects, ii) air interface, iii) medium access, iv) networking, v) testbeds & prototyping. Finally, a number of future challenges and the respective open research topics are described.

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Section: A Phy and Mac: Software Defined Radio (Sdr) Basedmentioning

confidence: 99%

Satellite Communications in the New Space Era: A Survey and Future Challenges

Kodheli

Lagunas

Maturo

et al. 2021

IEEE Commun. Surv. Tutorials

600

428

View full text Add to dashboard Cite

show abstract

“…Finally, (16) translates into an algorithm that recursively calculates the codeword by processing m bits at a time. By implementing this algorithm in hardware it is possible to increase the output data throughput of the BCH encoder by a m factor over the standard serial solution.…”

Section: B Parallel Bch Encodingmentioning

confidence: 99%

“…Previous research works, notably [7] and [16], elucidate the architecture of a DVB-S2 FEC system, comprising a BCH encoder and a LDPC encoder, a Bit Interleaver, and a Constellation Mapper. While [7] implements both VCM and CCM modes and employs a parallel BCH encoder, [16] exclusively supports CCM mode and adopts a serial BCH encoder with a conventional LFSR architecture.…”

Section: State Of the Artmentioning

confidence: 99%

“…The modulo-2 addition is performed with XOR gates, represented in Figure 6 with a two-input bus XOR. Each bus width is BTDATA which is equal to the parallelism m. The computed BTADTA bits are now concatenated with the other 192 − BT DAT A bits of the present state, to form the p(T ) + x m term defined in (16). Now to calculate the future state p(T +m) the vectormatrix product with the state matrix Q m is performed by the combinational network in Figure 6.…”

Section: B Bch Encodermentioning

confidence: 99%

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Design and Implementation of a DVB-S2 Reconfigurable Datapath BCH Encoder for High Data-Rate Payload Data Telemetry

Quintarelli,

Bertolucci,

Nannipieri

2023

IEEE Access

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“…Reference [9] proposed a serial BCH encoder and a parallel LDPC encoder, both of which support 21 different DVB-S2 code configurations, but they are not cascaded for FEC system-level design and validation. Reference [10] designed a BCH-LDPC cascade encoder that supports a single code length 64800 and code rate 1/2, but the data throughput is limited due to its serialin and serial-out hardware architecture, which cannot meet the requirement of high-speed applications. In [11], parallel implementation of BCH and LDPC encoders was proposed and static random access memory (SRAM) was employed to store check bits, therefore both row and column addresses are required to search parity-check bits corresponding to the parallel information bits, which increases the complexity of address management and the controller.…”

Section: Introductionmentioning

confidence: 99%

An Efficient FEC Encoder Core for VCM LEO Satellite-Ground Communications

Kang

Wang

2020

IEEE Access

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A powerful forward error correction (FEC) scheme based on the serial concatenation of Bose-Chaudhuri-Hocquenghen (BCH) and low-density parity-check (LDPC) codes has been adopted by the second generation digital video broadcast (DVB-S2) standard due to their near Shannon limit performance. This paper proposes an efficient FEC encoder core to support different DVB-S2 codes for variable coding modulation (VCM) schemes of low earth orbit (LEO) satellite-ground communications. By exploring the properties of different concatenated BCH-LDPC codes and reusing the computation units and memories, the compatibility is achieved and the utilization of hardware resources is improved. Besides, parallel computing is performed to speed up the acquisition of check bits, which allows the encoding throughput to be increased. Hardware architecture implementation on Xilinx XC7K325t field programmable gate array (FPGA) shows that the encoding throughput rate of the proposed FEC encoder core can reach 1.19 Gb/s. And the overall data throughput is improved by 30.9% compared with the constant coding modulation (CCM) schemes.

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FPGA Implementation of FEC Encoder with BCH & LDPC Codes for DVB S2 System

Cited by 11 publications

References 1 publication

Satellite Communications in the New Space Era: A Survey and Future Challenges

Satellite Communications in the New Space Era: A Survey and Future Challenges

Design and Implementation of a DVB-S2 Reconfigurable Datapath BCH Encoder for High Data-Rate Payload Data Telemetry

An Efficient FEC Encoder Core for VCM LEO Satellite-Ground Communications

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